Monthly Archives: October 2012


Copper (Cu) Wire Bonding Technical Benefits Overview

We love copper (Cu) wire. In fact, we already described in our post “Copper Wire (Cu) Reduces Package Cost” the cost advantages of copper wire bonding compared to Gold (Au) wire. Copper wire introduced some challenges to assembly houses (such as ASE, Amkor, STATS ChipPAC) but also offers a few technical benefits, in addition to cost.


ASICs utilizing copper wire bonding can offer the same quality level, reliability and performance as those using gold. Copper wire delivers the same electrical characteristics as gold wire, but it offers lower resistance (R) which can be beneficial for certain applications which are sensitive to IR drop for example.


Despite the benefits and substantial industry know-how on Copper wire, gold wire is still benefiting from a long track record of success (many decades) and deployment of billions of ASIC devices. Therefore, Gold (Au) wire is still enjoying a huge circle of trust by being a reliable material.



Resistance (R)  – Copper (Cu) wire vs Gold (Au) wire


Wire bonding length defines the resistance, capacitance, and inductance of the wire. Long wire bonds can be critical to the overall package performance.


In applications where resistance can improve performance, using Copper (Cu) wire can offer real technical benefits. Furthermore, Cu wire reduces heat dissipation within a package.


Copper wire offers better resistance than gold wire.



Capacitance (C)  – Copper (Cu) wire vs Gold (Au) wire


There are no drawbacks on Cu wire capacitance:

Copper wire self capacitance is nearly the same for Gold (Au).



Inductance (L)  – Copper (Cu) wire vs Gold (Au) wire


There are no drawbacks on Copper wire inductance:


Self inductance is nearly the same for Gold (Au) and Copper (Cu) wire.


Copper wire bonding is widely adopted in the industry and gaining acceptance in all market segments including the automotive industry. In the leading assembly houses copper wire has become the preferred material for wire bonding interconnects.


Copper wire bonding offers better performance and lower cost. With these benefits there is no doubt that within 5-10 years gold wirebonds will be a rare material in the assembly house.


Copper Wire (Cu) Bonding Reduces Package Cost

Do you know someone that is not eager to reduce their ASIC production costs? I don’t.  Some say that redesign changes can lead to significant cost reduction, for instance – using a more advanced silicon technology node to shrink the die size. True, but this is a really big, painful step with many implications. How about a much simpler method that will let you cut 5% to 15% of your assembly cost? Copper (Cu) Wire Bonding!

A relatively new technology in the package domain, called copper (Cu) wirebonds, involves a simple and straightforward modification to exiting gold-based packages. Whether you use a QFN or BGA wirebond based solution, a simple change could save you lots of money in the long run and allow price optimization from day one.

Until now, the majority of wirebond packages were based on gold (Au) wires, and to be honest, everybody was very pleased. However, the increases in gold prices have resulted in many ASIC suppliers confronting a yearly price increase in their assembly costs.



In fact, assembly houses have already started specifying the gold price level as part of price quotations of Au wirebond-based package. This allows them to correct the package price when the gold price goes up.

While Cu wire introduces a few technical benefits, the main driver of copper wire in the industry is cost.

Overall the copper wire technology is 3 years in full production and over 15B devices have been shipped.  Most of the top 4 packaging houses are already supporting cu wirebond technology and will be able to help you save 5%-15% of your package cost.


Does size matter? Understanding Wafer Size

Silicon wafers are the most essential element in the realization of ICs. The semiconductor industry had invested heavily to increase the wafer size during the last 30 years, so while foundries used to produce 1 inch wafers, today’s common wafer size is 300mm (11.8 times larger than 1 inch). There is a clear plan to move towards a 450mm wafer size (1.5 times larger than 300mm).

Increasing wafer size is not a trivial process. As a matter of fact, silicon wafer manufacturing technologies were re-engineered in order to achieve the technology necessary to increase the wafer size during the years. It is difficult to grasp the amount of capital invested in the size growth innovation. My guess is around a triple-digit Billion USD.

Why does wafer size matter?

A larger wafer diameter enables producing more semiconductor devices from a single wafer, enhancing productivity and efficiency. If foundries would still produce 1 inch wafer today, there is no chance they’d be able to support the volume of smart-phones, tablets and PCs.

Common Mistake: 300mm wafer is NOT 12 inch!

Wafer diameter was traditionally noted in inches, but today’s ‘correct’ figures use millimeters and they describe the wafer diameter; the following table shows the correct size of the wafer.

One of the common mistakes in the  industry is the actual physical size of the 300mm and 450mm wafers. Many seem to automatically use the inch metrics and announce “12 inch” and “18 inch” accordingly.

This is absolutely incorrect. A 300mm wafer is actually 11.8 inch.

So next time you hear someone referring to 12 inch wafer, use this info to correct the misunderstanding.


BGA Substrate Design

Very often IC package design requires designing a BGA substrate. Substrate design and layout is very similar to any other PCB design. The difference is that the substrate size is much smaller than most of the PCBs you have seen. In this post we do something a bit unusual and recommend a Free EDA tool (FREE!).

The substrate is a small PCB located inside the BGA package. Substrate design consists of layout of all signals from the package balls to the wirebond pads (in case of Wire Bond) or to the bump pads (in case of Flip-Chip).

Whether the BGA substrate design is done by the assembly house or by an external company specializing in substrate layout, you will need a tool to review the work as part of the development and sign off process.

Cadence has a free tool, called Allegro, which is very helpful for this task.


The Cadence® Allegro® FREE Physical Viewer allows you to view and plot databases from Allegro PCB Editor, Allegro Package Designer, and Allegro PCB SI technology.



Download here:

We are very happy with the tool.  It’s easy to use and offers all the required features to review the substrate design.

You can consider the Allegro as an MCM file viewer.

What is an MCM File

As the EDA market evolved and created various file extensions, the IC package design guys got the MCM extension — it the IC Package Design File format . The MCM file describes the package outline, the substrate layout and the pads.

It’s basically the same format as a .brd file which is used for PCB designers, but intended for IC packages. Currently, MCM file is a de-facto standard for package design database and the majority of the package/assembly houses will send out MCM files for review.