Monthly Archives: February 2013

A Simple Method for Choosing ASIC Design Services

In 2005 I applied for a job in Singapore. The job required some technical and business skills and therefore the interview was a bit tricky.

One part of the interview related to estimating market size. They asked me to estimate the number of Piano Tuning companies which are currently active in Tokyo, Paris and New Zealand. For the young readers, these are usually one-person company that tunes clients’ piano at their homes. Tuning is not required very often, maybe only every 1-2 years.

There are many things to consider here. First: culture. How popular is the Piano in those areas. Second: Finance. Can these people afford a Piano? Moreover, I know that houses in Japan are relatively small. Is there a place for a Piano in the house? I had just too many puzzles in my head and I only had 3 minutes.

Eventually I was wrong and did not get the job.

It would have been easier to find the answer if I was more familiar with the music industry or particularly with the Piano market. And it would have been a piece of cake, if I was a Piano tuning guy myself, right?

This brings me to a very interesting discussion around evaluating RFQ responses from ASIC design services.

In some scenarios you may consider outsourcing your ASIC design activities to an external company.  Most of the fabless companies occasionally use external ASIC design services because they lack internal resources.  The other type of companies, which are product companies, must use external services because their core competencies are not around semiconductors.

Like in my piano story, the question is how do you evaluate ASIC design companies, which may be far away from your domain expertise? The answer is obviously the all-too-familiar RFQ.

chip design


While there are really many ASIC design companies out there, you should send out your RFQ or chip specifications to no more than 5 companies. Dealing with more than 5 vendors during the early exploration phase will consume too much energy and will slow you down.

You should look for a development team that brings great value and minimizes the project risk. A team which is ‘spot on’ your project requirements. One indication that I use, is comparing the schedules provided by the different design houses. Naturally, there will be a few companies with a very optimistic schedule and a few with a very pessimistic schedule.

Over the years I developed my own metrics. My rule of thumb is as follows: ASIC design companies that acquired relevant experience and can reuse some of the blocks from their previous projects will hand over the shortest schedule. And chip design companies which have no relevant experience will propose the longest schedule and thus also the highest risk.

In short, my recommendation is – look at the schedule and use it as an indicator to assess your risk.

Like in any other rule there are exceptions. If you are planning a very complex chip utilizing leading edge technologies it could easily take 5 years of development and 3 tape-outs iterations. But all in all, it’s very similar to my piano story –  it’s either guessing the way or knowing the way.



Lead Frame Overview and Custom-Lead Frame Benefits

The name leadframe (or lead-frame) is actually very accurate.

Leadframe is an alloy frame that consists of the package leads and the paddle. The silicon die is attached on the paddle and the leads are connected to the die with wirebonds. That’s it.

In the following photo you can see the paddle (center) which is typically used for ground signal and many leads around the package stretching from the package edge to a point where the wirebonder can reach.

Many types of packages are based on leadframe, such as QFN, QFP, LQFP, TQFP, PLCC, SOIC and TSOP.

Like any other material, leadframe requires tooling. The tooling can either be open tools,which are available and can be used free of charge, or custom tools that are associate with an NRE cost.

Leadframes are produced in a long strip, which allows them to be quickly processed on assembly machines.



Open Tool LeadFrame

Packaging houses have many leadframes tooling on stock that can be available for your project. Therefore, it is wise to look around and ask several packaging houses whether they have open tools for your leadframe.  This will save you the NRE required for creating the tooling.


Custom LeadFrame

If open tools are not available then you’ll have no choice but to pay for a custom leadframe.

But, there are also some technical issues that may require the use of a custom leadframe:

For most application the length of the bond wire is not critical and there is no need to have a custom leadframe.

But for some designs, particularly RF applications, the length of the wirebonds may be vital. With a custom leadframe you can determine the distance between the die and the leads to achieve the exact wirebond length required.

In cases where the chip is too small for the selected package, a custom leadframe is needed to ensure the length of the wirebonds does not exceed the maximum length allowed by the package design rules.


Six ways to improve chip yield rate- before the project starts

Early on in Chip projects, yield is not taken very seriously. The common thinking goes –  anyhow there isn’t much to do as this early point of time. However, there are actually several things you can do even before the Chip design starts, which will translate to clear savings.

Calculating Yield

1- Know your Yield

Yield has a great deal of impact only if production volume is high. If you plan to manufacture only a few tens of thousands of components, perhaps yield is not the most important topic in your project’s plan.

Yield can be roughly calculated or estimated before the project has even started. Yet, if you have calculate a yield target of 95% there is no reason to invest money and efforts to try improving the yield from (the calculated) 95% to 99% because that would not be possible.  Therefore, it is important that you have calculated your yield and set that as a goal.

2- Consider Foundry Applicability

Semiconductor foundries are not taking any yield losses. It is not the fab responsibility whether your yield is high or low because they sell wafers and not dies. Therefore you should select the foundry the suits best to your Chip domain.

If you chip requires small node geometries go to GLOBALFOUNDRIES, TSMC etc. If you chip needs excellent RF performance go to: IBM, TowerJazz etc. The foundry can help you calculating the wafer yield based on their own process technology. If you can provide them with die size, number of layers, process node and options, they should be able to provide you with a very accurate yield figures for your project.

3- Match Design Team Experience to Your Project

If you have decided to outsource the frond-end and physical design activities to an external vendor, the main yield-related risk here is experience. If the design team does not have the relevant experience that matches your chip project (for instance: RF, High Voltage) you are really wasting your time. Don’t hire analog designer without high voltage experience if you need to design a 120V chip.

4- Select Silicon Proven IPs

More and more companies are shopping for Semiconductor IPs to help reduce time to market and minimize engineering cost. There are many IP vendors with high quality products and some with lower quality. The keyword here is risk minimization. You really want to make sure the IP blocks you are about to purchase and integrate into your chip are bug free and have been silicon proven and qualified for your process. Ask for test results and references.

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5- Follow Package Design Rules

For simple QFN packages there are no real concerns besides following the assembly house design rules. However complex packages can reduce yield dramatically. If your chip uses a package that consists of a multilayer substrate with high speed signals, this substrate should be considered as part of the silicon die. Improper routing of high speed signals, for example, will make the substrate performance very marginal and thus result in failures during final test.

6 – Say No to Tight Test Limits, Say Yes to Better Hardware

The only place to measure yield is at the testing phase. And this is done by the ATE.

Great ASIC engineers often try to over-engineer the chip design and as a by-product also tighten up the test result criteria. These limits will have direct impact on your profit. Every device that fails to meet limits during the screening process will be scraped. Therefore, don’t create the perfect test specification. Make one that meets your system requirements.

Loadboards, sockets and probecards have different quality levels and therefore different cost. But since these are the actual physical interface between your chip and the tester, you want to make sure they have the right quality and durably to allow solid connectivity to the tester during the test period. Otherwise, lower quality hardware will shave off your yield figures. Sockets for example, have limited number of insertions; you therefore should buy a socket that meets your chip production volume. Bottom-line — don’t compromise on the quality of the hardware interfacing your chip.


There is so much more to write on this topic, we promise to write more articles in the future. Stay tuned.



Introduction to HTOL

HTOL (High Temperature Operating Life) is a stress test defined by JEDEC to define the reliability of IC products, and is an essential part of chip qualification tests. This post provides a high-level overview of HTOL. Obviously you should refer to the standard if you intend performing testing.


To predict reliability and operating life of IC products, JEDEC has defined a stress test that exposes the IC to extreme temperature conditions. Test results are then used to predict the long term failure rate of the IC.


An HTOL test is performed in an oven with 125C degrees, while the ICs are activated with dynamic signals and the VCC pins with max voltage. The details are specified in the following table.



JEDEC Standard JESD22-108, JESDS85
Temperature T>=125C
No. of Lots 3
No. Devices per Lot 77
Duration 1000 hours
Accept criteria 0 fails


After the HTOL stress test is completed the ICs must go through electrical screening to determine how many devices passed or failed the stress test. The JEDEC requirements define zero failures as an acceptable criterion, with test results defined in terms of FITs (failures in time). One FIT symbolizes one failure in 109 device hours.


To perform the HTOL test, all ICs must be in an oven, ideally placed in sockets and located on a PCB. Both sockets and burn-in-board must be able to withstand the high temperature during the test.


HTOL stress test


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