Monthly Archives: January 2015


How to Design and Make a Custom Analog IC in 44 Days

Recently we worked with a customer that had an urgent need to get a custom analog ASIC (application specific integrated circuit) developed in a very short time. The customer needed a completely working system in the first quarter of 2015. Working backwards from their system schedule they realized that they would need to have working silicon by the end of the year. The customer came to this realization in September of 2014.





Others Said “ASIC Design That Fast is Impossible!?!?!”

The designers began making their rapid ASIC prototyping request to various custom ASIC companies and what they got back was rather disappointing. You see, a typical custom IC development can take 9 to 12 months to deliver first prototypes. Clearly these times would not work and in fact they were too slow by 7 to 10 months!


Triad Said “We Can Do It. Let’s Get Started!”

The customer reached out to Triad and we explained that with our patented Agile ASIC™ technology we could deliver custom analog ASICs on their requested schedule.  The calendar for the project is shown below. The major milestones for the project are identified with the letters (A), (B), (C), and (D) on the the calendar.



Triad Semiconductor 44 Day Analog ASIC Project Calendar

(A) Agile ASIC Project Kick Off – 10/22/14

This Agile ASIC project started with a project kick-off meeting on October 22, 2014. At this meeting, the customer worked directly with Triad ASIC engineers to define the requirements for their ASIC. Following the kick-off meeting,

Triad’s IC designers got busy with two parallel paths.

One designer started working on the circuit level design using circuit IP from Triad’s extensive library.

The second designer simultaneously began the floor planning and layout of the complete chip using Triad’s patented Agile ASIC Tiles™. We will talk more about this process later but at high level Agile ASIC Tiles are IP that contain circuit elements and configurable routing fabric. These tiles can literally be ‘snapped together‘ during the floor planning process.

(B) Base Layers Tape Out – 11/13/14

In a radically new approach to chip design, Triad “taped out” or sent the IC design to the foundry well before the circuit was complete. Triad’s Agile ASICs utilize a patented via configurable methodology. Any of the analog or digital circuitry in an Agile ASIC can be reconfigured by changing a single via layer.

A custom IC consists of up to 30 mask layers with each layer taking 1-2 days of processing at the foundry. Normally, an ASIC cannot released until the entire design has been completed and fully simulated.

Triad’s agile approach allows the ASIC to be released early so that layers can be processed at the fab in parallel with the designers still working on circuitry and simulation.

(C) Via Layer Tape Out – 12/4/14

On December 4th, we taped out a mask for a single via-layer representing the circuit and routing between circuit elements. Since only this one via mask layer need be processed, the time left to get the chip through the foundry was only a couple of days. After fabrication was completed, wafers containing the ASIC die were shipped to a package house. At the package facility, the wafer was split into individual ASIC die. Each die was then placed into a QFN plastic package.

(D) Delivery of Working Agile ASIC Prototypes – 12/24/14

After the devices were packaged, they were overnight shipped to Triad’s facilities for testing and then devices were shipped to the customer for integration into their system for evaluation.

Custom Analog ASIC Project Milestones


What is an Agile ASIC™

Triad Semiconductor is North America’s premier supplier of mixed signal custom ASIC solutions. We design and manufacture custom analog and mixed signal ICs to customer specification. We are experts at full custom design and we have patented reconfigurable technology that is bringing true agility to the custom IC design process.

An Agile ASIC contains mixed signal resources that can be configured and interconnected by making a single mask layer change. An Agile ASIC contains analog and digital IP that is overlaid with a patented global routing fabric. Wafers containing Agile ASIC die are partially processed and staged at the semiconductor foundry. Only a single via mask layer need be changed to completely alter or reconfigure the functionality of the die.

Agile ASIC Benefits


  • Major reduction in development time – Turn a one year effort into a 44 day quick turn project
  • Fastest possible time to market
  • Quick re-spin capability – 20 to 30 days
  • Mitigated project risk – re-use proven IP and via reconfigurability
  • Future proof – update design with a single via layer changed based on market feedback


This is a guest article by Reid Wender has been leading Triad Semiconductor’s marketing and application engineering groups since 2005. Prior to joining Triad, Reid was VP of Engineering for the Semiconductor Division at QuVIS, a leading digital cinema company. He has 20 years of ASIC design and project management experience at companies including Nextwave Silicon, ASIC International, Philips, and IBM. He holds a BSEE from the University of Tennessee.


ASIC Clock Jargon: Important Terms

Clock to an SoC is like blood to a human body. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the SoC. There are many terms which modern designers use in relation to the clock and while building the Clock Tree, the backend team carefully monitors these. Let’s have a look at them.



  • Clock Latency: Clock Latency is the general term for the delay that the clock signal takes between any two points. It can be from source (PLL) to the sink pin (Clock Pin) of registers or between any two intermediate points. Note that it is a general term and you need to know the context before making any guess about what is exactly meant when someone mentions clock latency.
  • Source Insertion Delay: This refers to the clock delay from the clock origin point, which could be the PLL or maybe the IRC (Internal Reference Clock) to the clock definition point.
  • Network Insertion Delay: This refers to the clock delay from the clock definition point to the sink pin of the registers.

Consider a hierarchical design where we have multiple people working on multiple partitions or the sub-modules. So, the tool would be oblivious about the “top” or any logic outside the block. The block owner would define a clock at the port of the block (as shown below). And carry out the physical design activities. He would only see the Network Insertion Delay and can only model the Source Insertion Delay for the block.


Having discusses the latency, we have now focus our attention to another important clock parameter: The Skew.


We shall now take the meaning of terms: Global Skew and Local Skew.


  • Local Skew is the skew between any two related flops. By related we mean that the flops exist in the fan-in or fan-out cone of each other.
  • Global Skew is the skew between any two non-related flops in the design. By non-related we mean that the two flops do not exist in the fan-out or fan-in cone of each other and hence are in a way mutually exclusive.


In the next post we would discuss the implications of big clock latency on the timing.



This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India. To read more blogs from Naman, visit



Image credit: ckaiserca 


What’s wrong with RTL for ASIC designs?

I think this is an appropriate first post, because this is a question that we’ve heard many times when talking with hardware engineers trying to sell our product. The fact that there are (now) about a dozen companies trying to replace RTL with alternatives (I’ll talk about HLS in other posts) should be proof enough that there actually are other ways to design hardware than RTL.


So first, what is RTL? Register Transfer Level. This means that you describe a digital circuit as registers + combinational logic (the logic is the ‘transfer’ between registers). This is higher level (and also a lot more convenient) than gate level, or transistor level. So what is wrong with it? Well for me the two main problems are:


  1. Lack of a model of computation. For instance, if you take software languages, the majority of them (with the notable exception of functional languages of course, and a few other esoteric languages) target a von Neumann architecture, meaning that the implementation of the program will read words from memory, perform computations, and write back words to memory. All RTL says is really ‘move data from register to register passing through combinational logic’. Common elements in hardware architectures such as RAM, ROM, FIFO, Finite State Machines (FSM or finite automaton) must all be described manually, relying on the synthesizer for correct inference.
  2. Semantics is implicit. In a way this is due to the lack of model of computation, but not only. This issue is present, too, when using assembly language instead of a high-level language. Say you want to declare a synchronous register. Well you can’t do that. You declare a register, but it is the way you use it that will ultimately make it synchronous or not: you have to assign it in a process/block with ‘if rising_edge(clock)’ or ‘@(posedge clock)’. You cannot declare a FSM, instead you must declare a register that takes enumerated values, which you must be careful to update in every path of your design. Like when writing assembly, you never declare a loop; you just jump to the same location several times in a row until the loop is done.


There is another issue with RTL hardware design, but it has as much to do with the level of description itself as with how the hardware is described. Two languages have been dominating the world of design for years, they are VHDLand Verilog. While they are pretty good to describe RTL hardware, they have many limitations:


  • Every time you declare a scalar, you must say the range of bits. For instance, a 9-bit variable can go from bit 3 to bit 11. Same thing when you declare an array.
  • The type system varies from very strong and restrictive (VHDL) to weak and flexible (Verilog). In both cases it will surprise you (and not in a good way) if you are not careful.
  • There are many ways to do the same thing. For example, initialization of signals: you can say ‘initial value of X is 5’ and when resetting the circuit, you can say ‘initial value of X is 18’. You have two or three different ways to design asynchronous logic. You have blocking and non-blocking assignments, but it is sometimes accepted to use one in the place or another, which will sometimes cause unexpected behavior (see one of the excellent posts by Jan Decaluwe on this, e.g., etc…


These limitations, combined with the limitations of tools themselves, are the main reasons behind the so-called coding styles that dictate how you should write your design if you want it to be properly synthesized. Examples are you should not set initial values to signals outside reset blocks, integer computation should use signed/unsigned in the numeric_std package in VHDL, a N-bit scalar should be declared with a N-1 down to 0 range (and a M-entries array with 0 to M-1 range), etc.


So this is a summary of what is wrong with RTL (and also with VHDL/Verilog) in my opinion. If you prefer to stick to RTL design, or you’re actually fond of VHDL or Verilog, good for you. If you are looking for improvements, however, I’ll explore alternatives in a future post.


This is a guest post by Matthieu Wipliez CTO of Synflow, an innovative EDA company based in Europe.

mlm wafer calculator

ASIC Price Calculator

The ultimate ASIC calculator is available live on AnySilicon’s  website. Together with our Die Per Wafer calculator this ASIC price calculator provides a very accurate final price for ASICs. Please note, we did not include shipping cost therefore you may want to add this to the total prices.

Wafer Click here to get wafer price quote
Wafer Sort Click here to get test price quote
Package Click here to get package price quote
Final Test Click here to get test price quote

As always, if you need Wafer Price, Package Price or Test Price, use AnySilicon to reach our to vendors and get competitive prices for different suppliers.

mlm wafer calculator

Die Per Wafer Calculator

Die Per Wafer (DPW) online calculator is free and available live on AnySilicon website. The die per wafer calculator is simple to use and very accurate, however the results are estimates.




Now when you have the number of dies per wafer, you may want to consider:


See here the list of semiconductor foundries


Get 3 price quotes from semiconductor foundries


Calculate final ASIC cost