Monthly Archives: February 2016

Semicondcutor packaging history featured

Semiconductor Packaging History and Trends


Since the invention of the first semiconductor package in 1965, the semiconductor packaging technology has grown dramatically and several thousands of different semiconductor package types have been made. The chart below presents the semiconductor packaging history. Particularly it shows the two major trends in semiconductor packaging:  addressing high pin count and accommodating small footprint requirements.


Most semiconductor devices today are enclosed in a package to prevent damage to the die and the connecting wires. But if you ask any ASIC engineer or a Purchasing manager Semiconductor packaging is an undesired adder to the silicon die. It increases the total chip area, increases the total cost and decreases the electrical performance of the silicon die. But semiconductor packaging has also some substantial advantages.


Semiconductor package enables electrical connection between the silicon die and the PCB. The package helps fanning out the dense die pads into larger area so PCB layout and assembly can be made easily.


In power hungry applications the semiconductor package responsibility is to dissipate the heat produced by the silicon die to a large surface, such as heat sink. This allows the die to continue operate normally in high temperature environments.


Semicondcutor packaging history doubled



The First Semiconductor Package


Three engineers from Fairchild: Don Forbes, Rex Rice, and Bryant Rogers invented a 14-lead ceramic Dual-in-Line Package (DIP) with two rows of pins. This was the first real semiconductor package. DIP packages came into volume production in early 70’s.


High Pin Count Semiconductor Packaging


In the 80’s, chips became larger and integrated more functionality. A chip with 1 million gates was introduced and the semiconductor packaging technology had to address the increasing number of IOs. This was the reason for introducing PGA (Pin Grid Array) and BGA (Ball Grid Array) packages.


Addressing the high IOs was driven mostly by high-end SoCs used for computing, networking, and storage application when large data or address buses are needed for transferring data in and out the chip. The struggle in these type of applications is balancing between size, power dissipation and cost.


In the beginning, every BGA/PGA package was based on a ceramic substrate but today laminate is a primary source for both low cost and high end applications. Laminate is a low cost solution for BGA substrates that can support both low and high performance applications.


In the 90’s the CSP (Chip Scale Package) was introduced to address both high pin count and small size requirements. The CSP package is essentially a small size BGA with smaller ball pitch.



Small Size Semiconductor Packaging


In the 90’s the second trend in semiconductor packaging has started and it was all about miniaturization. This trend was obviously driven by mobile devices such as laptop and mobile phones which demanded “near die size” type of packages in order to eliminate package cost and area.


Due to these requirements several packaging technologies were introduced. QFN package was introduce as a type of CSP (Chip Scale Package) and since, QFN package has become the most successful package type because of its simplicity, performance and price.


WLCSP (bumping) package type was also developed and it’s currently the smallest size package because  the package size equal the die size.


Semicondcutor packaging history


Download this chart by using this link.


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asic design

Simple Analog ASIC Design Solves Difficult Thermal Analysis Problems

In a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. These chips are being built on smaller lithographies, running at higher speeds, dissipating more power and to make things worse, they are being encapsulated in ever decreasing package sizes. What could possibly go wrong?


Plenty! Higher device performance comes at a price; higher temperatures. And with higher temperatures comes lower reliability if thermal considerations aren’t carefully controlled. Semiconductor manufacturers have long been aware of the problems associated with heat. Most have application notes and white papers plastered across their web sites espousing the benefits of careful calculation of power management using their values of ΘJA and ΘJC (Junction-to-Ambient and Junction-to-Case thermal resistance, respectively) often with sidebars suggesting various heat sinks to use in marginal situations. This puts the burden of solving temperature related problems on the backs of the user.


Recent technology advances and the proliferation of the use of Thermal Test Chips like those developed by JVD, Inc. for Thermal Engineering Associates of Santa Clara, CA is allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production.


Thermally Engineer Your Own ICs


Today, almost anyone can design a thermally engineered IC. Whether you’re a designer at a commercial semiconductor company or you’re crafting your own ASIC, the tools are readily available to physically simulate the thermal effects of your design, well in advance of spending any money to produce your first silicon prototypes. Thermal Test Chips (TTCs) allow system designers to fully model, measure and modify their designs before committing to costly silicon.

TTCs are special silicon die (yes, they are Analog ASICs) that are used to model and measure the thermal performance of your chip design in situ before you commit those tooling dollars for masks and wafers. Modeling allows you to create multiple individual heat sources on the TTC die, identical to the heat sources that will occur on your final IC. Temperature sensors, strategically located throughout the TTC give you precise measurement of the temperature of the die at multiple locations simultaneously. The heat sources can be modulated to replicate various portions of your IC being power on, off or in an intermediate mode. By tracking the absolute or changes in temperature at any point on the TTC, you can determine if one or more heat sources combine to exceed safe operating temperatures of the intended IC design. If temperatures are problematic, you can go back to your IC design and modify the chip’s layout to isolate the heat sources and alleviate the potential problem.


How It’s Designed


TTCs are produced like any other Analog ASIC. In this example, the individual Unit Cell is 2.5mm x 2.5mm and each cell contains two heat sources (metal film resistors) and four strategically located temperature sensors (diodes). See Figure 1a and 1b.

A basic TTC Unit Cell schematic


Figure 1a: A basic TTC Unit Cell schematic. Note the strategic placement of the temperature sensing diodes.

A basic TTC Unit Cell layout.

Figure 1b: A basic TTC Unit Cell layout. Each cell has two heat source resistors (show in orange) that occupy 86% of the die area contained within the electrical contact pads. Four temperature sensing diodes shown in green.


It is rare that a thermal analysis would need to be performed on a die as small as 2.5mm x 2.5mm. For this reason, all of the cells on the wafer are interconnected, forming a wafer scale product. This is important because thermal modeling and measurement must be done with a die that closely approximated the size (mass) of the IC being simulated. The wafer scale product can then be sawn into any of hundreds of different die configurations, ranging from a single cell die (2.5mm x 2.5mm) up to an array die that is 10 cells by 10 cells (25.68mm x 25.68mm) or even larger, to obtain a size commensurate with the IC being simulated.


How It Works


Metal film resistor heat sources were chosen for their better uniformity and matching across the wafer compared to polysilicon resistors. Additionally, their relatively stable temperature coefficients of ± 20ppm/°C results in constant power dissipation over the course of the thermal measurement.


The heat sources are laid out to occupy 86% of the die area, thus conforming to the JESD51-4 standard. Each heat source has a pair of contacts for power connection and a second pair of contacts for Kelvin (e.g., 4-wire) connections to measure precisely the voltage being applied to the heat source. Similarly, each of the temperature sensing diodes also have Kelvin connections, allowing one pair of connections to provide just enough forward current to operate the diode at the break of its forward current-voltage curve, while the second pair of connections can accurately measure the forward voltage. It is critical to keep the current below the point of self-heating, yet above the point that can cause problems with repeatability. See figure 2a and 2b.

Proper measurement current

Figure 2a: Proper Measurement Current, IM,shown above, corresponds to the diode’s forward current-voltage curve.


Kelvin Connections

Figure 2b: Kelvin connections for the temperature sensing diodes (center diode connected in this example).


Creating and Configuring Arrays of TTCs


There are two basic concepts in creating and configuring TTCs; uniform heating and distributed heating. Uniform heating implies that the heat source is consistent across the surface of the die, eliminating any thermal gradients across the silicon surface. To achieve this, the resistances in each TTC must be dissipate the same heat and therefore must be passing the same heating current. By configuring the TTCs in the correct series, parallel or series-parallel combination, uniform heating is achieved.

For example, figure 3 (below) shows how the two heating elements in a TTC can be configured either in parallel (for a heater resistance of 3.8Ω) or in series (for a heater resistance of 15.2Ω).

Unit Cell 1x1 array
3x5 TTC array

Most chip designers strive to achieve an end product whose silicon die aspect ratio is 1:1. Occasionally this isn’t possible due to I/O requirements (bonding pad locations). When an asymmetrical TTC array is needed, consideration should be given to the aspect orientation of the array. For example, thermal simulation of a die that is 13mm x 8mm can be achieved by using a TTC array that is 5 x 3 cells or 3 x 5 cells.


Both contain the same number of cells and, therefore can dissipate the same amount of power and both offer a center diode for temperature sensing. For uniform heating, both operate the same and the only difference would be the voltage and current needed to generate the same amount of power dissipation. For example, see figure 4. The 3X5 array has 5 series strings of resistors with each string having a resistance of about 37.5 Ohms (= 5 X 7.5 Ohms). Paralleling these strings results in a total resistance of about 6.25 Ohms. For 10W of power dissipation, a voltage of 7.9V @ 1.265A would be required.


The 5X3 array, shown in figure 5, has 10 series strings of 3 resistors with each string having a resistance of about 22.5 Ohms (= 3 X 7.5 Ohms). Paralleling these strings results in a total resistance of about 2.25 Ohms. For 10W of power dissipation, a voltage of 4.74V @ 2.1A would be required.


5x3 TTC array


Either approach works but the preference is to go with the lower current alternative since it is less stressful and will require smaller trace widths on the board where the packaged chip is mounted.

Distributed heating is actually more representative of what one might expect to see in a large ASIC or ASSP. Certain parts of the circuit that are designed for higher speed or must manage greater power are expected to dissipate more heat. Chip designers will want to know how hot these hot spots actually get and how the heat might affect circuitry on another area of the chip that might have some sensitivity to heat, such as a precision voltage reference.


individual cells can be powered to simulate high power dissipation portions of the IC

TTCs are designed to accommodate either wire-bond or bumped wafer flip chip packaging. In the wire-bond configuration, the pads surrounding each TTC are connected to their adjacent neighbor with metal. Only when the die is sawn into its desired configuration (2×2, 5×5, 7×9, etc.) is the connection severed. Conventional wire bonding techniques pretty much limit package pinout access to only those pads around the periphery of the array. Due to the way the masking is done on the wafers, the maximum chip size of wire bond chip version, is a 40X40 array, (1,600 TTCs occupying a total of 10,000mm2 ~100mm X ~100mm).


When an application calls for a more localized heating, for power mapping purposes, the flip chip design is ideal. With no internal interconnects between the TTC in the array, all bonding pads are accessible. For example, for an 8 x 8 TTC array, heat can be generated at selected cells. See figure 6.


Unit Cell specifications for each TTC are important to understanding the overall expected performance of the array being used to simulate the new IC under development. See figure 7.


In addition to single chip packages, TTCs can also be obtained in custom stacked die configurations (see figure 8) as well as multi-chip (horizontal layout) packages and package on package components. Custom packaging services are also available for those requirements that cannot be addressed by the standard packages described above.

wire bond 1x1 chip mounted on wire bond 2x2 chip

wire bond 1x1 chip mounted on wire bond 2x2 chip

TEA recently introduced a new TTC Unit Cell size version that is 1mm X 1mm and contains a single heating resistor and a single temperature sensing diode. The smaller Unit Cell allows for greater power mapping capability. Both TTC Unit Cell sizes are available in 150mm (6”) diameter wafer form as well as sawn array chips.



Using Re-Distribution Metal


An RDL (Re-Distribution Layer) is used to redistribute the electrical contact pads – either wire bond or bump – into a configuration other than that originally designed on the chip. Some reasons for this are:


 Redistribution layer to align bonding pads
  • Mounting a chip onto BGA package substrate originally designed for a different chip pad configuration;
  • Wire bond chips may have a single row of wire bond pads in the center of the chip.
  • Stacked chips may require all wire bond pads along one chip edge.

The process for creating an RDL on the wafer consists of creating one or more metal layers between insulation layers. The metal layers are etched to form traces that connect the existing chip contact pads to created new pads in desired locations. Depending on the trace routing complexity, there will be multiple layers of metal and insulator stacked upon one another. The new pads can be used for wire bonding connection or act as the base for adding Flip Chip bumps.Figure 9 is a TTC-1002 2X3 array with an RDL that provides for wire bonding either along specific locations on the periphery or down the center of the chip. The RDL is a custom requirement that needs to be discussed in detail with TEA before any implementation can begin.


How Hot Is Hot?

 Calculating power density using empirical data derived from Thermal Test Chips, IC designers and packaging engineers can model the actual performance of a product well in advance of committing a design to silicon or a package to hard tooling. Semiconductor process advancements are merging heretofore incompatible pieces of complex systems onto a single substrate. Gone are the days of isolating the power elements to their own heat sunk packages. Now they reside a few microns away from temperature sensitive structures. Something has to give. Or does it?


The use of Thermal Test Chips allows designers to precisely pinpoint the heat sources on their designs and simulate its effect on the performance of the entire system. Take the 2.54mm x 2.54mm Unit Cell discussed earlier. With its two 7.6Ω resistor heating elements, each capable of handling 1 Amp at 6 Volts, the cell can dissipate 12 Watts of power. Its area (6.45mm2) yields a power density of 186W/cm2. The newly introduced 1mm x 1mm Unit Cell with its single 10.5Ω resistor heating element, capable of handling up to 0.55 Amps at 5.5Volts, can dissipate 3 Watts of power. Its area (1mm2) yields a power density of 300W/cm2.


Combining Unit Cells into an array derates these figures slightly due to the additional silicon required for saw streets between the cells. For example a 10 x 10 array of the 6.54 square mm cell has a power density of 182W/cm2, while a 10 x 10 array of the 1 square mm cell has a power density of 261W/cm2. These are exceptionally high PDs and are difficult to achieve by other means.


In power mapping applications, these high PDs per unit area offer the user an opportunity to better simulate power density levels resulting from multi-point localized heating in high performance CPUs and ASIC chips. Additionally, they can better simulate high power and high frequency transistors – SiC (Silicon Carbide) and GaN (Gallium Nitride).


Although seldom discussed in public journals , the use of these Analog ASIC Thermal Test Chips play an important role in allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production.


This is a guest post by:  JVD is a privately-held company founded in 1982 whose mission is to achieve analog performance in their customers ASIC designs. Whether an ASIC, ASSP, or SoC design, JVD’s differentiated analog approach allows its customers to compete successfully in consumer, wireless, high-speed computing, power management, medical, industrial and networking applications. For more information, please visit



New 2D Semiconductor Material Will Lead to Faster Chips

Research in the field of 2D materials that started approximately five years ago, focusing on developing materials that are one layer thick which would make it faster for atoms to move in a single layer. Currently, transistors and other components used in electronic devices have been made of 3D materials such as silicon, which is much slower than using 2D materials. These 3D materials consist of multiple layers on a glass substrate in which electrons bounce around inside the layers in all directions. The problem with this is that the electrons tend to scatter amongst the layers which slows down the speed of electronic devices.


A group of researchers, led by Ashutosh Tiwari and comprised of doctoral students K. J. Saji and Kun Tian, and Michael Snure of the Wright-Patterson Air Force Research Lab near Dayton, Ohio among others, at the University of Utah have discovered the first stable P-type 2D semiconductor. This semiconductor consists of the element tin and oxygen, also known as tin monoxide. It is only one atom thick which allows electrical charges to move through it much faster than it would have using the typically used 3D materials such as silicon.




The new 2D semiconductor tin monoxide could be used in transistors. Transistors are the main part of electronic devices, such as computer processors, graphics processors, and mobile devices, that makes them functional. This new semiconductor will also make it possible to manufacture transistors that are smaller and faster than transistors that still make use of 3D materials such as silicon.


The smaller size would make processors much faster and more powerful. This is because a chip’s speed depends on how many transistors are packed into it. Since the 2D transistor is much smaller, more transistors would be able to fit into a single chip. The researchers predict that this innovation will make electronic devices up to 100 times faster.


The processors will also stay cooler for longer. Since the electrons move in a single layer the amount of friction will be less than with 3D transistors where they bounce around in multiple layers. 2D transistors will also take less power to run, which is greatly beneficial for devices that run on battery power.


It will be a great asset for medical devices such as electronic implants. These implants would be able to run for longer on a single battery. This will lessen the medical costs of those who have to have these implants replaced often and would increase the efficiency of the implants.


Commercially, these new 2D transistors would lead to computers and smartphones that are much faster. These computers and smartphones would also be able to run on battery power for much longer than devices using 3D transistors.


Tiwari estimates that they will be able to produce a prototype device within two or three years.

rd spenders feature

Semiconductor R&D Growth Slows in 2015

Semiconductor industry spending on research and development grew by just 0.5% in 2015, which was the smallest increase since the 2009 downturn year and significantly below the compound annual growth rate (CAGR) of 4.0% in R&D expenditures during the last 10 years, according to IC Insights’ new 2016 edition of The McClean Report.  The half-percent increase nudged worldwide R&D spending by semiconductor companies to a new record-high level of $56.4 billion in 2015 from the previous peak of $54.1 billion set in 2014, says IC Insights’ flagship market analysis and forecast report on the IC industry.


Growing concerns about the weak global economy, slumping sales in the second half of the year, and unprecedented industry consolidation through a huge wave of merger and acquisition agreements weighed on semiconductor R&D spending in 2015.  The new 2016 McClean Report shows Intel continuing to lead all semiconductor companies in R&D spending in 2015, accounting for 22% of the industry’s total research and development expenditures.  The top 10 R&D ranking is shown in Figure 1.



Pro 14 Top semiconductor r&d spends 03.02.16

Get here a high resolution image


Following Intel in the 2015 R&D ranking are Qualcomm, Samsung, Broadcom, and the world’s largest wafer foundry, TSMC.  The top five spenders were unchanged from 2014, but below that point, the rankings of most companies were shuffled.  Micron Technology moved up to sixth in 2015, swapping positions with Toshiba, which fell to seventh in the new ranking.  MediaTek went from ninth in 2014 to eighth place, while SK Hynix climbed from 12th to ninth in 2015.  ST slid from eighth in 2014 to 10th in 2015, and Nvidia fell out of the top 10 to 11th place in 2015.


The top 10 in the R&D ranking collectively increased spending on research and development in 2015 by about 2% compared to the half-percent increase for total semiconductor R&D expenditures in the year.  Combined R&D spending by the top 10 exceeded total expenditures by the rest of the semiconductor companies (about $30.8 billion versus $25.6 billion) in 2015—something that has continued to hold true since 2005 and probably well before that, according to The 2016 McClean Report, which becomes available in January 2016.


Figure 1


Intel’s R&D expenditures grew 5% in 2015, which is significantly below its 13% average increase in spending per year since 2010 and slightly under its 8% annual growth rate since 2001, the new report says. Underscoring the growing cost of developing new IC technologies, Intel’s R&D-to-sales ratio has climbed significantly over the past 20 years.  In 2010, Intel’s R&D intensity level was 16.4% of revenue spent in research and development compared to 24.0% in 2015.  Intel’s R&D-to-sales ratios were 14.5% in 2005, 16.0% in 2000, and just 9.3% in 1995.


With worldwide semiconductor sales falling nearly 1% in 2015 to $353.6 billion and R&D spending rising 0.5% to $56.4 billion, the industry’s R&D-to-sales ratio grew slightly to 16.0% from 15.8% in 2014.  Since 2000, the semiconductor industry’s annual R&D-to-revenue ratio has average 16.0%.  The new McClean Report forecasts semiconductor R&D spending to grow about 4% in 2016 $58.9 billion and reach $76.3 billion in 2020, which would represent a CAGR of 6.7% from 2015.  By between 2016 and 2020, the semiconductor industry’s R&D-to-revenue ratio is expected to average 16.4% compared to 16.2% in the 2011-2015 time period.




This is a guest post by IC Insignt. To review additional information about IC Insights’ new and existing market research reports and services please visit:


RF Package Design Focusing Portability

Today, the (SiP) System-in-Package approach offers a new dimension to system integration, far beyond mere dense micro-packaging of existing System on Chip solutions. Not only does SiP offer the capability to integrate almost any kind of companion passive component with a given active circuit, but it also enables flexible combinations of analogue circuits and RF functions with digital integrated circuits.

The SiP (System-in-Package) approach is a key driver for the miniaturization trend for portable devices (Cell-phones, PDAs, Ultra-miniature PCs), particularly with respect to the growing number of RF functions that need to be integrated. Most SiP design methodologies, that include integrated passive components, rely on fixed libraries of components that are locked to a particular substrate supplier and stack-up.



For high volume consumer devices it is increasingly important to ensure that any given SiP can be sourced from at least two independent manufacturers. The novel design methodology that is presented in this paper is aimed at allowing easy transfer of integrated passive circuit design from one supplier to another and even from one technology to another (e.g. LTCC to IPD).


The methodology is based on a user extendable library of mechanical objects for which the electrical models are created automatically for a given stackup and/or technology. Thus any design that is initially made for a particular supplier can easily be re-tuned for an alternative source. The second manufacturer can have a completely separate set of electro-mechanical parameters (stack-up, dielectric constant, layer thickness, loss factors, metal types) and may even use an alternative technology. The paper will illustrate the design method with some examples of RF SiP designs that have been ported between LTCC suppliers and between LTCC and IPD technologies.


The SiP approach to RF system integration has become essential to the miniaturization roadmap for nomadic devices. Despite a long term tendency to integrate more and more functions within a single semiconductor (SoC approach) the never ending increase in functionality for small personal devices continues to drive the use of SiP to make complete systems. RF SiP can be realized using a multitude of technologies; for each technology a range of suppliers offer different materials, physical dispositions and properties, that require any design to be matched to the particular supplier. In this paper the following technologies are considered: Organic multi-layer laminate with small SMTs, Ceramic multi-layer substrates (LTCC), Integrated Passive Devices (using thin film on silicon or glass), a combination of the above.


An example of an RF SiP is shown in Figure 1.



High volume RF SiP should be at least double sourced. In order to use 2 different supply chains the design must be adjusted to take into account
the differences between the suppliers. In certain situations it may be necessary to use 2 different supply chains using different SiP technology
This paper describes a universal RF SiP design methodology that is sufficiently flexible to allow for a design to be transferred rapidly between
different technologies or between suppliers using the same technology.


The design methodology developed at Insight SiP has already been described in previous communications. The methodology is summarized in Figure 2.


The method uses a combination of circuit and electromagnetic simulation tools to create a design progressively from basic schematic representation to a complete 3D electromagnetic representation of the layout. Manufacture is only carried out on a design for which the completed layout has been fully simulated; 2.5D or 3D electromagnetic simulations are used for the passive integration (laminate, LTCC, IPD) and harmonic balance or Spice modelling for the active circuits. The complete design flow from initial schematic based circuit simulation to fully simulated and tested layout is shown in Figure 3.



RF SiP uses a combination of Organic Laminate substrates, Ceramic LTCC substrates and Thin Film Silicon or Glass IPDs. Each technology and each supplier may be characterized by a technology file that describes the material parameters and physical disposition between the dielectric and metallic layers. In the case of organic and ceramic laminates each supplier has a range of materials and layer structures that may be used. Figures 4 to 6 show typical technology files for LTCC, IPD and Laminate options.


Figure 4: Typical LTCC Technology File

Figure 5: Typical IPD Technology File

Figure 6: Typical Laminate Technology File


In order to fully characterize each technology for simulation purposes it is essential to have a minimum set of data. This should include dielectric material properties for all layers (εr, tanδ at operating frequency), conductivity for all metallic and resistive layers plus the mechanical dimensions. In addition to the basic nominal parameters, the manufacturing tolerances allow yield predictions and worst case corner analyses to be carried out.

Mechanical Objects

The methodology described above allows any of the above technologies to be designed using the same basic flow. The functionality that is contained within buried functions inside the substrate is created using an iterative process. For each technology a range of parameterized mechanical objects has been created. These objects allow simple RF functions, such as capacitors, inductors and resonators, to be created. A couple of typical mechanical objects are shown in Figure 7 and Figure 8.


Figure 7 Typical IPD Mechanical Object


Figure 8 Typical LTCC Mechanical Object


It should be noted that at this stage the mechanical objects do not have a direct link to the material properties, nor to the vertical stack of the particular technology and supplier that is to be used. These objects can therefore be reused if a design is transferred between 2 suppliers. Objects having similar electrical functions in different technologies have been created. This allows a design carried out using one technology to be transferred to another (For example LTCC to IPD or vice versa).


Furthermore the creation of new mechanical objects is quite straightforward so that new novel designs can be created by this methodology.


The second step in the design process is to couple the technology file for the target process to the mechanical objects. A series of batch based electromagnetic simulations of the mechanical objects within the desired technology file framework creates data for a look-up table based model for each component (L, C or more complex resonator element).


This process is very easy to repeat with a new technology file, facilitating design transfer between suppliers and technologies. Figure 9 shows the schematic image of the LTCC coupled line resonator of Figure 8.


Figure 9 Schematic Object Linked to Mechanical Object


Closed Loop EM design

The process described above allows for the creation of a set of project and technology related schematic objects that can be optimized to produce the required RF functionality. Simulations using these models can be carried out in both the frequency domain and the time domain (Spice or Harmonic Balance).


At this level of the design, circuit optimization is carried out to determine the parameters of the schematic/mechanical object. This process is quite similar to that carried out in semiconductor design using library based objects that have electrical performance and create layout.


The next step of the process is to create complete sections of physical layout with the mechanical objects using the circuit optimization parameters. A closed loop iterative process is used to obtain final layout that has the same electrical performance as the sum of the modelled portions. At this stage coupling effects between blocks are compensated for.

This has the advantage of allowing the mechanical objects to be placed close together without any risk of causing unseen effects. This makes the designs created by this method more compact than those using a “P Cell” approach with large keep-out zones to avoid coupling.

Portability to Different Technology Files

As indicated above the design methodology naturally allows for portability between technology files. In order to re-design for an alternative supplier, using the same technology, the process employs the same mechanical objects with a new set of technology values. This process starts from the same basic schematic and simply re-optimizes the parameters of the objects to compensate for the new physical and mechanical parameters. The final EM close loop process is then carried out to create new layout for the new supplier.

In order to change from one technology to another, equivalent mechanical objects that have similar functions in both technologies have to be created. In this case the same basic schematic is used and the schematic/mechanical objects are swapped. Thereafter the process is similar to the normal design flow.

Design Portability

In order to illustrate the process 2 examples are given. The first case considers the transfer of a Bluetooth filter design between different LTCC suppliers. The second case considers the transfer of a filter design between LTCC and IPD technology.

LTCC to LTCC supplier


In this example a 3 pole 1 zero filter that is designed for a Bluetooth module to fit under the active components has been designed using the methodology to operate with one LTTC foundry and has been successfully transferred to a second one. The filter is designed using semi-distributed transmission line resonators with resonator coupling to create a suitable frequency zero in the response.

The 2 LTCC stacks are compared in Figure 10.

 Figure 10 LTCC Stacks


As can be seen the stacks and material properties of the 2 suppliers are quite unalike. Despite this the mechanical objects were converted from one stack to the other and the design process completed rapidly. The completed EM tuned filters for both stacks are compared in Figure 11.


It can be noted that the 2 filters are quite similar but the physical dimensions of the filters are slightly different to compensate for the LTCC stack differences. Electrical performance for both realisations was similar.

LTCC filter to IPD Filter

The above LTCC filter has also been transferred to an IPD technology. In this case the mechanical objects were quite different. The physical size of the standalone flip-chip filter is 2 x 2 mm compared to an LTCC size of 3 x 4 mm. Figure 12 shows the preliminary outline drawing of the filter, whilst figure 13 shows the electrical performance.


This paper has shown the utility of a mechanical object based design methodology for buried functions within RF SiP. Portability between suppliers and between technologies has been demonstrated.


About the Author

Chris Barratt

Insight SiP CTO

Chris is Engineering graduate from Cambridge and London Universities UK. He has 28 years experience in RF and Microwave design with specialization in filters and active circuits in thin film, thick film, laminate and LTCC. Prior to Insight SIP he was instrumental in setting up National Semiconductor’s Design Centre in Sophia Antipolis.

press release

SilabTech is the winner of IESA 2015 Technology Innovation Award

SilabTech, leading supplier of High Speed Interface intellectual property designs (IPs), announced today that it was awarded with the 2015 IESA Award for the Most Innovative Product for its High Speed Interface (SERDES) Design which is leading the industry in its Low Power figures while enabling customers to use it in wide variety of applications. The award was announced as part of IESA (Indian Electronic and Semiconductor Association) annual summit that had taken place in Bangalore last week. The IESA committee had looked at more than 100 nominees before awarding this prestige prize to SilabTech.



“Winning the IESA Award is a great recognition for our break-through work on Low Power solutions for High Speed Interfaces. SilabTech is operating in a highly demanding environment where Interface Speed is increasing dramatically at the time where customers are expecting Green solutions with lower power and lower silicon area- this is the toughest segment in Silicon IP”, said Sujoy Chakravarty CEO of SilabTech; “This industry recognition is announced at the time where we win several high profile projects with Industry leaders that will integrate SilabTech solutions as part of their next generation products.”


“Technovation Awards celebrates excellence and recognize role-models in the electronics and semiconductor ecosystem”, as stated by M.N Vidyashankar, President,IESA who further commented that “Team SilabTech winning the award in the Product Innovation category shows just how great products can come out of India and are adopted by global players in the semiconductors space”


During the IESA summit event, SilabTech had demonstrated its USB 3.0 and 3.1 SERDES IP Cores that support the newest Type C Connector on advance nodes for the PC, Storage and Consumer Electronics markets. SilabTech also demonstrated its solution for the Data Converters market based on the JESD204B SERDES and Controller (1- 12.5Gbps).



Media Contact:

Payal Chakraborty, Manager-Marketing Communications

+91- 9945342044