An Introduction to On-Chip Variation (OCV)

On Chip Variation (OCV) is an increasing problem that starts at 130nm and its effects are increasing with smaller process nodes. And On-Chip Variation (OCV) is one of them, specifically for Static Timing Analysis.

The first task is to find all possible sources variation, and find out how these can affect a delay of a cell and hence, timing.

In this article I will focus on the various sources of on chip variation:

Etching

Let’s look into the below layout of an inverter (which also shows the Width (W) and Length (L) parameters of an inverter)

….and, a chain of inverters (this is mostly the case of clock path, be with me for upcoming posts and I will exactly let you know, why OCV is mainly applied on clock paths, 50% should be clear from the term “chain of inverters”)

We use photo-lithography fabrication technique to build the inverters on Silicon wafer, and this is a non-ideal process, where the edges will not exactly be straight lines, but there will be disturbances. And why so, because the above technique needs photo-masks which are created using etching, which is again non-ideal. Below is how the ideal mask and real mask look like

Now these variations on the sides, is also dependent on what logic cell is present on either sides of this inverter, if its surrounded by chain of inverters on either sides, the variation on the sides will be less as the process parameters to build mask for a chain of similar size inverter, is almost the same. But, if the inverters are surrounded by other gates, like flip-flops, then the variation will be more.

With that said, the below inverters in the middle will have a similar and less variations

and the inverters on the boundaries will have different and more variations. (observe the difference in actual mask, in above image) And guess what…. this directly impacts the drain current below, as it is proportional to (W/L) ratio

These OCV values he should be used it in STA analysis and see its (+ve or -ve) impact.

As we were identifying sources of variations, and below is the second one

Oxide Thickness

Let’s go back to the inverter layout and look which part are we talking about. Here, we are talking about gate oxide thickness variation

If we go by ideal fabrication process, below is what you will achieve, a perfectly cubic shape (below is the 2D image, so it looks rectangle) oxide layer, and perfectly deposited metal gate or polysilicon gate

But, if we go by actual oxidation process, it’s very difficult or almost impossible to achieve the above perfect oxide thickness.

Below is what you will actually get

So, what’s wrong having above oxide thickness. Again, it’s the drain current (which is a function of oxide thickness, shown in below image) that will get varied for the complete chain of inverter, especially, the ones on the sides. The variations in middle inverters will still be uniform.

Imagine a chain of, as long as, 40 inverters or buffers…. the variation is HUGE. And this needs to be accounted for, in STA.

So the challenge is, how to we find the range and effectively model it in STA.

The below image models “low-to-high waveform condition” at input of CMOS inverter, in terms of resistances and capacitances. So, overall, it’s the RC time constant that actually decides the delay of a cell

With above, we can safely say, the propagation delay tPD is a function of ‘R’

We see variation in drain current ‘Id’ due to variation in ‘W/L’ and ‘oxide thickness’ variations, and above we see, how propagation delay is function of ‘R’. The question is now, what next? If I am, somehow, able to prove, that drain current ‘Id’ strongly depends on ‘R’, then I can directly relate (W/L) and oxide thickness variation to ‘R’, and below images will exactly do that

Hence, every inverter in the below chain, will have delay which is different than the immediate next one, something like below

If we plot a Gaussian Curve with delays on x-axis and no. of inverters on y-axis, it will give us a clue, about the peak variation in inverter delays, the minimum and maximum variation in inverter delays like below

Now, we know the percentage variation in delays of inverter compared to ‘100ps’, because that’s where the inverter delay (with used ‘W/L’ ratio) is expected to be, and most number of inverters on chip with that ‘W/L’ ratio have a delay of 100ps.

OCV variation is +8% and -9% and one of them will be used for launch and other for capture in setup/hold timing calculations. For eg. for setup calculation, the launch clock will have OCV of +8% and capture clock path will have OCV of -9%. That means, if the original clock cell delay is ‘x’ in launch clock, with OCV into account, the same clock cell delay will be (‘x’ + 0.08x). This calculation in setup takes into account the On-Chip Variation, and that’s where the name comes from, as shown in above image.

This is a guest post by Kunal Ghosh with http://www.vlsisystemdesign.com/

Taiwan Maintains Largest Share of Semiconductor Wafer Fab Capacity

IC Insights recently released its new Global Wafer Capacity 2017-2021 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2021.  Figure 1 splits the world’s installed monthly wafer production capacity by geographic region (or country) as of December 2016.  Each regional number is the total installed monthly capacity of fabs located in that region regardless of the headquarters location for the companies that own the fabs.  For example, the wafer capacity that South Korea-based Samsung has installed in the U.S. is counted in the North America capacity total, not in the South Korea capacity total.  The ROW “region” consists primarily of Singapore, Israel, and Malaysia, but also includes countries/regions such as Russia, Belarus, and Australia.

Figure 1

As shown, Taiwan led all regions/countries in wafer capacity with 21.3% share, a slight decrease from 21.7% in 2015 when the country first became the global wafer capacity leader.  Taiwan was only slightly ahead of South Korea, which was in second place.  The Global Wafer Capacity report shows that South Korea accounted for 20.9% of global wafer capacity in 2016, slightly more than the 20.5% share it held in 2015.  Two companies in Taiwan and two in South Korea accounted for the vast share of wafer fab capacity in each country.  In Taiwan, TSMC and UMC held 73% of the country’s capacity while in South Korea, Samsung and SK Hynix represented 93% of the IC wafer capacity installed in 2016.

Japan remained firmly in third place with just over 17% of global wafer fab capacity.  Micron’s purchase of Elpida several years ago and other recent major changes in manufacturing strategies of companies in Japan, including Panasonic spinning off some of its fabs into separate companies, means that the top two companies (Toshiba and Renesas) accounted for 64% of that country’s wafer fab capacity in 2016.

China showed the largest increase in global wafer capacity in 2016, rising 1.1 percentage points to 10.8% from 9.7% in 2015. China’s gained marketshare came mostly at the expense of North America’s share, which slipped 0.9 percentage points in 2016. With a lot of buzz circulating about new ventures and wafer fabs in China in the coming years, it will be interesting to watch how quickly China’s installed wafer capacity grows.  It is worth noting that China first became a larger wafer capacity holder than Europe in 2010.  The two companies with the largest portion of wafer fab capacity in China were SMIC and HuaHong Grace (including shares from joint ventures).

In total, the top five wafer capacity leaders accounted for more than half of the IC industry’s wafer fab capacity, having increased from 2009, when the top five wafer capacity leaders accounted for approximately a third of global capacity.

Moving towards Context Aware Verification (CAV)

The race between predictions vs. achievement of Moore’s law has had multi-fold impact on the semiconductor industry. Reuse has come to the rescue both from the design and verification viewpoint to help teams achieve added functionality on a given die size. This phenomenon lead to the proliferation of IP & VIP market. Standardization of interfaces further enables this move by shifting the product differentiation towards architecture and limited proprietary blocks. To enable continued returns and cater to different application segments, the IP needs to be highly configurable.

Verifying such flexible IP is a challenge; integrating it for a given application and ensuring that it works, further complicates the problem. Given that verification already claims majority of the design cycle efforts, it is important to optimize on the resources, be it tool licenses, simulation platform or engineer’s bandwidth. A focused attempt is required so as to ensure that every effort converges towards the end application i.e. the context in which the design would be used irrespective of the flexibility that the silicon offers. This refers to the subject Context Aware Verification (CAV)!

Verification space has been experiencing substantial momentum on multiple fronts so as to fill the arsenal of the verification engineer with all sorts of tactics required for the challenges coming our way. While these developments are happening independent of each other, they seem to converge towards enabling CAV. Let’s take a quick look at some of these techniques –

Traditionally, test plan used to answer what is to be verified until constrained random entered the scene where how to verify, what to verify and when are we done needs to be addressed by the verification plan. Today verification planner tools enable us to develop executable verification plan with the flexibility to tag the features based on engineer who owns it or based on milestones or based on priorities and above all based on any other custom definition. This customization is useful to club features with reference to a particular context or configuration in which the IP can operate. With this information, the end user of the IP can channelize his efforts in a particular direction rather than wandering everywhere thereby realizing CAV in the larger scheme of things.

Apart from coverage goals that get defined as part of the vplan, there is a need of a subset of tests that would achieve these goals faster. What this means is that the test definition needs to be –

– Scalable at different levels (IP, sub system & SoC)

– Portable across platforms (constrained random for block level, directed tests for SoC verification & validation)

– Provide a possibility of tagging the tests w.r.t. a given configuration viz a set of valid paths that the design would traverse in the context of a given application.

Graph based verification is a potential solution to all of this. There is a need to standardize the efforts and to enable discussions in this direction Accellera has initiated Portable Stimulus Proposed Working Group. Once there is a consensus on the stimuli representation, selection of a subset of tests targeting a given configuration would further boost CAV.

With design size marching north, the simulation platform falls short in achieving verification closure in a given time. A variety of emulation (HW acceleration or prototyping) platforms provide an excellent option to speed up this process based on the design requirements. While the verification teams benefit from the simulation acceleration, these boxes also help in early software development and validation. The shift left approach in the industry is enabling basic bring up of OS and even simulating real time apps on these platforms much before the silicon is back. Ability to run the end software on the RTL brings further focus and is an important step towards achieving CAV.

Once all these technologies reach maturity a combined solution would bring in the required focus in the context of the end application.

As Chris Anderson said – “In the world of infinite choice, context – not content – is king!

Our designs with myriad configurations are no different. It is the context that would bring in convergence faster making those products that follow this flow as king!

_____________________________________________________________________

This a guest post by Gaurav Jalan, general chair at DVCON India

ARM Acquires two companies: Mistbase and NextG-Com

Just last summer, the NarrowBand-IoT (NB-IoT) standard was approved and now ARM has announced the acquisition of two companies in the field: Mistbase and NextG-Com.

The acquisition “will save the industry years of development effort and improve access for developers by reducing the time it takes to get products approved by standards bodies and network operators,” according to ARM’s wireless business GM Paul Williamson, as posted on the company blog.

Based in Sweden, Mistbase is focusing in developing wireless communications solutions in the field of IoT. The company is 1.5 years old and came out of Lund university.

NextG-Com based in UK and India, and provide wireless and satellite communication market partners with specialist engineering services around critical core components to help gain earliest entry to emerging new markets.

Through this acquisition, ARM will enable cellular modem to IoT and other applications.

Semiconductor Major Product Categories Growth 2016-2021

Sales of memory ICs are expected to show the strongest growth rate among major integrated circuit market categories during the next five years, according to IC Insights’ new 2017 McClean Report, which becomes available this month.  The 20th anniversary edition of The McClean Report forecasts that revenues for memory products—including DRAMs and NAND flash ICs—will increase by a compound annual growth rate (CAGR) of 7.3% to \$109.9 billion in 2021 from \$77.3 billion in 2016.

The 2017 McClean Report separates the total IC market into four major product categories: analog, logic, memory, and microcomponents.  Figure 1 shows the forecasted 2016-2021 CAGRs of the four major IC product categories compared to the projected total IC market annual growth rate of 4.9% during the five-year period.  As shown, the memory IC category is forecast to show the strongest growth rate through 2021 while the weakest increase is expected to occur in the logic category, which includes general-purpose logic, ASICs, field-programmable logic, display drivers, and application-specific standard products.

Figure 1

The strong memory CAGR is driven by surging low-power memory requirements for DRAM and NAND flash in portable wireless devices like smartphones and by growing demand for solid-state drives (SSD) used in big-data storage applications and increasingly in notebook computers.  Moreover, year-over-year DRAM bit volume growth is expected to increase throughout the forecast to support virtualization, graphics, and other complex, real-time workload applications.

Analog ICs, the second-fastest growing segment, are a necessity within both very advanced and low-budget systems.  Power management analog devices are critical for helping extend battery life in portable and wireless systems and have demonstrated strong market growth in recent years.  In 2017, the signal conversion market is forecast to be the fastest growing analog IC category, and the second-fastest growing IC product category overall, trailing only the market growth of 32-bit MCUs.

Total microcomponent sales have cooled significantly.  Fortunately, marginal gains in the cellphone MPU market and strong gains in the 32-bit MCU market have helped offset weakness of standard PC and tablet microprocessor sales.

Semiconductor R&D Spending: Intel accounted for 36%

Intel continued to top all other chip companies in R&D expenditures in 2016 with spending that reached \$12.7 billion and represented 22.4% of its semiconductor sales last year.  Intel accounted for 36% of the top-10 R&D spending and about 23% of the \$56.5 billion total worldwide semiconductor R&D expenditures in 2016, according to the 20th anniversary 2017 edition of The McClean Report that was released in January 2017.  Figure 1 shows IC Insights’ ranking of the top semiconductor R&D spenders based on semiconductor manufacturers and fabless suppliers with \$1 billion or more spent on R&D in 2016.

Figure 1

Intel’s R&D spending is lofty and exceeded the combined R&D spending of the next three companies on the list. However, the company’s R&D expenditures increased 5% in 2016, below its 9% average increase in spending per year since 2011 and less than its 8% annual growth rate since 2001, according to the new report.

Underscoring the growing cost of developing new IC technologies, Intel’s R&D-to-sales ratio has climbed significantly over the past 20 years.  In 2010, Intel’s R&D spending as a percent of sales was 16.4%, compared to 22.4% in 2016. Intel’s R&D-to-sales ratios were 14.5% in 2005, 16.0% in 2000, and just 9.3% in 1995.

Among other top-10 R&D spenders, Qualcomm—the industry’s largest fabless IC supplier—remained the second-largest R&D spender, a position it first achieved in 2012.  Qualcomm’s semiconductor-related R&D spending was down 7% in 2016 compared to an adjusted total in 2015 that included expenditures by U.K.-based CSR and Ikanos Communications in Silicon Valley, which were acquired in 2015.  Broadcom Limited—which is the new name of Avago Technologies after it completed its \$37 billion acquisition of U.S-based Broadcom Corporation in early 2016—was third in the R&D ranking. Excluding Broadcom’s expenditures in 2015, Avago by itself was ranked 13th in R&D spending that year (at nearly \$1.1 billion).

Memory IC leader Samsung was ranked fourth in R&D spending in 2016 with expenditures increasing 11% from 2015. Among the \$1 billion-plus “R&D club,” the South Korean company had the lowest investment-intensity level with 6.5% of its total semiconductor revenues going to chip-related research and development in 2016, which was up from just 6.2% in 2015.

Toshiba in Japan moved up two positions to fifth as it aimed its R&D spending at 3D NAND flash memories.  Foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) was sixth with a 7% increase in 2016 R&D spending, followed by fabless IC supplier MediaTek in Taiwan, which moved up one position to seventh with 13% growth in R&D expenditures. U.S.-based memory supplier Micron Technology advanced from ninth to eighth in the ranking with its research and development spending rising 5% in 2016.

Rounding out the top 10, NXP in Europe was ninth in 2016, slipping from sixth in 2015 and SK Hynix grew its R&D spending 9% to complete the list.   Fabless Nvidia just missed the cut with a 10% increase in expenditures for research and development.

Semiconductor consolidation played a factor in industry R&D spending rising just 1% in 2016 to a record-high \$56.5 billion after a 1% increase in 2015 to \$56.2 billion.  The slowdown in industry-wide R&D spending growth also corresponded with weakness in worldwide semiconductor sales, which declined 1% in 2015 and then recovered with a low single-digit increase in 2016.