Search Results for Latch-up

ALTER Technology

UK

Alter Technology are an OSAT providing assembly/packaging test and qualification services in the semiconductor industry.

IMMS GmbH

Germany

Design, verification, and test of analog, digital, and mixed-signal ICs. Specialized in biomedical and optical applications. Premium partner of X-FAB.

SYNERGIE CAD PSC

France

SEMICONDUCTORS BACK-END SERVICES: IC’s Testing, IC’s Packaging, IC’s qualification-Reliability, IC’s Supply Chain and PCB Design and Fabrication.

Sofics

Belgium

Sofics is an IP provider improving reliability of ICs through innovative designs. Sofics offers 3 products: TakeCharge®, PowerQubic® and CustomIO®.

Presto Engineering

France

Presto Engineering, provides ASIC design and outsourced operations for semiconductor and IoT device companies, helping its customers minimize overhead, reduce risk and accelerate time-to-market.

SignOff Semiconductors

USA, India

SignOff Semiconductors is having best-in-class expertise in all aspects of ASIC / SOC Design Services from spec-to-silicon.

ON Semiconductor

USA

On Semiconductor Custom Foundry Services group offers a comprehensive portfolio of high performance mixed signal and high voltage (BCD and Bipolar) processes to external designers and fabless companies.

Advanced Silicon

Switzerland

Advanced Silicon is a fabless mixed-signal IC solution provider for High-Voltage, High-pin count, and ultra-low noise peripheral SOCs.

Aragio Solutions

USA

Founded in 2003, Aragio Solutions is a full-service provider of semiconductor intellectual property (IP) for integrated circuit (IC) design.

IC Failure Analysis Lab

USA

IC Failure Analysis Lab is a full-service provider of Failure Analysis and Qualification services to Semiconductors, Medicals, Telecommunications, and Automotive companies.

EAG, Inc.

USA

EAG's Microelectronics Test and Engineering team provides semiconductor and electronics design firms with test, debug, and early engineering support for new product introduction.

Eurofins | MASER

The Netherlands

Eurofins MASER is an independent engineering service company. Since 1993 we have offered Reliability Test and Failure Analysis Services to the semiconductor and electronic systems industry.

How to bulletproof your ASIC Design

As the ASIC design is moving towards maskset creation and tapeout, the cost of design changes are increasing exponentially.  It’s easier and cheaper to modify the ASIC design and even redo some of the chip architecture early the design stage. However it’s much more difficult and far more expensive after ...

Managing ASIC Qualification – A Quick Guide

Many IC designers pay little attention to ASIC qualification and consequently pay high price and delays before the chip reaches to high volume. The mindset of experienced IC designers is considering IC quality (and reliability) through all phases of the IC design process. Today, more than ever, re-tapeout is costly ...

AnySilicon Guidelines for Semiconductor IP Core Selection

The semiconductor IP core market has grown dramatically in the last 10 years. There are literally hundreds of IP core suppliers in the market providing almost every possible functionally -  from DC/DC and PLLs to Bluetooth and CPU cores. This large number of vendors and IP cores makes the selection ...

Sondrel innovating Verification

An often-overlooked part of chip design is Verification according to Sondrel as designing the front end of a chip is generally perceived as being the more interesting part. However, as Susan Mack, a Senior Engineering Manager at Sondrel, disagrees: “Verification is a very important part of the chip design process ...

The Ultimate Guide to RF-SOI

What is RF-SOI?   RF-SOI is name of a specialized semiconductor process utilized to create certain RF Integrated Circuits for applications like antenna tuners for cellphones and switching devices. Essentially, it is RF version of the SOI technology.   Historical Development and Evolution of RF-SOI Technology   Peregrine Semiconductor initiated the SOI process technology in 1990s ...

The Ultimate Guide: FDSOI

FDSOI stands for Fully Depleted Silicon on Insulator. FDSOI is a planar process technology that provides an alternative solution to overcome some of the limitations of bulk CMOS technology at reduced silicon geometries and smaller nodes.   The FDSOI process has two distinct features. First starting with the substrate, an ultra-thin buried ...

What Is Latch Up and How to Test It

Simply defined, Latch-Up in VLSI is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.   What is ...