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The Wafer Quiz – By AnySilicon

April 18, 2017, anysilicon

Depositphotos_64905389_m-2015 quiz

 

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Dolphin Integration announces the availability of the new generation 28 nm SpRAM generator

April 17, 2017, anysilicon

news

Launching any low-power SoC on a highly competitive market requires true differentiating factors. For IoT applications requiring ultra low-power solutions to extend battery life-time for wireless-connected devices, SoC architects optimize power modes by partitioning the SoC. This minimizes dynamic power in active modes, as well as power leakage in stand-by

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DDR4 Set to Account for Largest Share of DRAM Market by Architecture

April 14, 2017, anysilicon

ddr4

The new, higher-speed DDR4 DRAM generation gained significant marketshare in 2016, representing 45% of total DRAM sales. Previously, DDR3 DRAM, including low-power versions used in tablets, smartphones, and notebook PCs, accounted for 84% of total DRAM sales in 2014 and 76% in 2015, but in 2016, DDR4 price premiums evaporated

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Xcerra Corporation to be Acquired by Unic Capital Management

April 11, 2017, anysilicon

xcerra

Xcerra Corporation (NASDAQ:XCRA) and Sino IC Capital Co. Ltd. today announced that Xcerra and an affiliate of Sino IC Capital , Unic Capital Management Co., Ltd., have entered into a definitive agreement under which Unic Capital Management Co., Ltd., will acquire all outstanding shares of Xcerra for $10.25 per share

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Solido Launches Machine Learning Characterization Suite

April 06, 2017, anysilicon

machine learning

San Jose, CA – April 6, 2017 – Solido Design Automation, a leading provider of variation-aware design and characterization software, today announced the immediate release of its Machine Learning (ML) Characterization Suite. This new product uses machine learning to significantly reduce standard cell, memory, and I/O characterization time, helping semiconductor

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Hierarchical Sequences in UVM

April 06, 2017, anysilicon

Negotiation with lawyer who is sitting behind desk and has clasped hands on document.

Rising design complexity is leading to near exponential increase in verification efforts. The industry has embraced verification reuse by adopting UVM, deploying VIPs and plugging block level env components at sub system or SoC level. According to a verification study conducted by Wilson research in 2012 (commissioned by Mentor) the engineers spend ~60%

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