The battery is dead; long live power management.

September 08, 2015, anysilicon

The 52nd Annual Design Automation Conference (DAC52) at San Francisco’s Moscone Centre had a number of interesting power management announcements, making this one of the hottest topics of the show. SureCore unveiled its own low power SRAM technology, creating a great deal of interest and setting a new low power SRAM standard.  Having spent a full week time immersed in the latest technology, I thought it appropriate to consider how the industry sees the challenges of low power and the different approaches being adopted.


Before we look to the future, consider why power management is now the most critical issue for portable products and to paraphrase Bill Clinton, ‘It’s battery life, stupid’.  With the advent of the Internet of Things (IoT) and the emergence of wearable technology, power consumption and battery life have become paramount.  As healthcare-related IoT devices become a reality alongside lifestyle wearables specifically designed for health monitoring, the problem will become more acute.

The traditional approach to power reduction uses variants of operating voltage scaling to reduce power.  But this can no longer deliver the necessary improvements, forcing a move towards selective powering-down of functional blocks, which limits both device usability and flexibility.   The traditional sleep mode seen in laptop computers may enable faster boot-up, but usability in this mode is almost non-existent: A new, more intelligent mode of power management is clearly needed… and demanded.



Power is The New King

Battery powered devices, particularly for long-life applications, demand a power management approach that delivers greater intelligence, flexibility, and most importantly, a longer battery life.

Many vendors at DAC 52 were promoting power management as a key issue, but few were willing to venture how new power management regimes would operate.   Notably, sureCore led the charge, describing the challenge and how to tackle the problem with SRAM.


The challenge is coming from two different factions in our ‘always connected’ world.  As more features are integrated onto a single System-on-Chip (SoC) device, the amount of integrated memory also increases. By 2017, integrated memory, much of it SRAM, will consume over 70% of an SoC’s active area; and a similar amount of power if not carefully managed. The new generation of smart watches, led by Apple, have a recharging cycle measured in hours, some as low as eighteen[1]. It is clear that future wearables must deliver user functionality measured in days and weeks, not hours.



New Regime for Power Management

Taken together, here’s a bold prediction: The hot topics at DAC 53 and 54 will be effective and accurate power prediction and management tools.  EDA vendors will promote advanced analysis capabilities that can accurately estimate power across a complex set of operating conditions.   Devices will feature variable power consumption depending on the application demands; integrated, self-learning power management algorithms will become commonplace.


Why?  Because today’s power consumption controls based around ‘full’, ‘reduced’, or ‘stand-by’ power, selectable via software or hardware, offer insufficient granularity and flexibility. Emerging power management strategies, on the other hand, will incorporate automatic system-level power reduction schemes that deliver ‘just enough’ power to deliver application functionality whatever that may be.


Here’s how embedded SRAM addresses that scheme.  Within embedded SRAM, adjustable back bias, full speed, retention mode, and deep sleep power savings address some of the rudimentary elements of analog power management. Knowing that SRAM can consume up to 70% of the on-chip power, sureCore has developed a detailed understanding of power consumption (and waste).  By 2017, we anticipate that many of the leading EDA vendors will incorporate multiple-modal power consumption analyses into their mainstream tools.  Power adjustment will be thought of as a continuum from the lowest level of ‘hibernation’ to full-on high performance operation.


The sureCore Approach

At DAC, comments from customers, toolmakers, and competitors alike emphasized the industry drive towards power reduction.  Although few offered concrete solutions, the undercurrent of concern around the power problem convinces sureCore that our approach is well founded and beginning to achieve critical mass. However, the real proof will be the adoption of the approach and technology into real products. Several leading embedded manufacturers think so too.

In the meantime, sureCore continues to define the frontiers of low power memory in the confident certainty that the 70% SRAM power savings will be demanded by every wearable product manufacturer


This is a guest post by Duncan Bremner, CTO, SureCore.