How to bulletproof your ASIC Design

February 11, 2016, anysilicon

As the ASIC design is moving towards maskset creation and tapeout, the cost of design changes are increasing exponentially.  It’s easier and cheaper to modify the ASIC design and even redo some of the chip architecture early the design stage. However it’s much more difficult and far more expensive after tapeout had been done.


Some companies have been unfortunate to encounter defects in the chip after-market deployment when the ASICs are already part of a product/system —  in the field. Recalling systems back for analysis and repair is too expensive to any company.


With the help of today’s advanced ASIC verification tools and services together with in depth testing and system integration provided by ASIC validation boards and services most of the functional bugs can be detected and corrected in the lab. But some blocks inside the ASIC are not directly related to the chip functionally and they need to be tested as well.


Therefore it’s highly recommended to look for reliability problems on prototype batches (MPW) before going to full production. A quick reliability test will help expose issues in design, process, package and assembly.


The qualification tests recommended in the quick qualification are: HTOL, ESD and Latch-up




quick qualification

HTOL test, or high temperature operating life, will expose defects such as: Contamination, Oxide defects, Si defects, , Electro-migration and contact defects.


ESD test, or electrostatic discharge, will expose defects in electrostatic sensitivity.


Latch up test , will expose defects related to sensitivity to parasitic bipolar action.



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