Category Archives: ASIC Design

Setup/hold interdependence in the pulsed latch (Spinner cell)

December 12, 2014, anysilicon

setup- hold time

This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design service.

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The IP Blame Game

December 10, 2014, anysilicon


This is a guest post by Methodics that delivers state-of-the-art semiconductor data management (DM)  for analog, digital and SoC  design  teams.

The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers,

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Mixed Signal Design & Verification Methodology for Complex SoCs

December 08, 2014, anysilicon


This is a guest post by S3 Group that provides design, verification and implementation of the most complex IC solutions.

This paper describes the design & verification methodology used on a recent large mixed signal System on a Chip (SoCs) which contained radio frequency (RF), analog, mixed-signal and digital blocks on one chip.
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Medical ASIC Design for IoT: Meeting FDA Guidelines

December 01, 2014, anysilicon


This is a guest post from Neil Miller, Engineering Manager at Nuvation Engineering, a provider of complex electronic product development and design services.
In the past few years, the market for IoT devices has exploded, opening up a whole new world of possibilities for telehealth and medical applications. Advancements in sensor design,

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Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models

November 12, 2014, anysilicon

custome design

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place

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What Does It Cost You When Your SoC is Late to Market?

November 07, 2014, anysilicon


If your chip is late to market, it is costing you far more than you know.
Arteris conducted a survey of all its chip design customers to gain a more accurate grasp of the major concerns they have in their day-to-day operations and to gain a better understanding of what

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