Category Archives: ASIC Design

Mie Fujitsu Semiconductor and CSEM develop ULP solutions for IOT

May 09, 2016, anysilicon

CSEM

Mie Fujitsu Semiconductor Ltd (MIFS) and CSEM have penned a joint development agreement to cooperate in the development of Deeply Depleted Channel (“DDC”) and near/sub-threshold technologies for the IOT/Wearables market. The agreement encompasses the development of ultra-low voltage, ultra-low power standard cell libraries, power management cells and memories as well

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Speed in IC’s : A major concern

March 20, 2016, anysilicon

Sprinter leaving starting blocks on the running track. Explosive

Firstly let me ask what strikes your mind first when I say performance?
Intel started designing processors with MHz to GHz frequencies (Improving the performance of course, but if we see the advantage there might be some flaws too). Yes serially it was possible to send and receive the data

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Simple Analog ASIC Design Solves Difficult Thermal Analysis Problems

February 24, 2016, anysilicon

asic design

In a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. These chips are being built on smaller lithographies, running at higher speeds, dissipating more power and to

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How to bulletproof your ASIC Design

February 11, 2016, anysilicon

crystal ball

As the ASIC design is moving towards maskset creation and tapeout, the cost of design changes are increasing exponentially.  It’s easier and cheaper to modify the ASIC design and even redo some of the chip architecture early the design stage. However it’s much more difficult and far more expensive after

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FPGA vs ASIC, What to Choose?

January 30, 2016, anysilicon

FPGA vs ASIC feature image

This is a high level article for those who are debating whether to use FPGAs or ASICs and need some technical and commercial insight to help ease the decision process. Both technologies, ASICs and FPGAs are absolutely fantastic and have great benefits but it’s up to you to figure out,

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Low-Power SoC Design Integration Issues

November 06, 2015, anysilicon

lo power

As technology evolves, more functionality is being added on SOCs. At same time, pressure is building up to reduce operating and standby power. Today the market is focused on reducing power in wide spectrum of SOCs from CPUs, GPUs and Mobile not just IOT/wearable SOCs. Battery powered SOCs require

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