Category Archives: ASIC Design

Introduction to ASIC Design Flow

October 10, 2016, anysilicon


Today, ASIC design flow is a mature process with many individual steps. ASIC design flow process is the backbone of every ASIC design project. To ensure design success, one must have: a silicon-proven ASIC design flow, a good understanding of the ASIC specifications and requirements, and an absolute domination over

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Understanding Standard Cell Characterization

October 06, 2016, anysilicon


Cell characterization is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.
Why is cell characterization needed?
No digital chip is possible without cell models. These cell models are produced by cell characterization using commercial softwares like guna.

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HDL Design House Opens New Office in Thessaloniki, Greece

October 04, 2016, anysilicon


Belgrade, Serbia – October 4th, 2016 – HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, is pleased to announce the official opening of its new development center in Thessaloniki, Greece, to better serve and more efficiently handle the growing number

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Is Charge Sharing Silently Killing your ASIC Design?

October 01, 2016, anysilicon


Sharing is caring, unless it is as vital as required charge to function your ASIC design. As we move down from 20nm and below on designs with low voltages, charge sharing is quickly becoming mission critical problem in high performance custom ASIC designs using dynamic logic. Moderate charge sharing may slow down your circuits,

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Verification, Validation, Testing of ASIC/SOC designs – What are the differences?

September 18, 2016, anysilicon

Negotiation with lawyer who is sitting behind desk and has clasped hands on document.

If you are involved in any ASIC/SOC design life cycle, it is highly likely that you would have heard questions like – Have you verified a feature?  Is all feature testing completed?  How will you validate a new feature?  What design defects were found and how?
The terminologies Verification,

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Understanding Your ASIC’s Age

August 03, 2016, anysilicon

Elderly man's face falling apart. Aging concept

This is an interview with Oliver King about understanding your ASIC’s age. As Moortec’s CTO, Oliver has been leading the development of compelling in-chip monitoring solutions to address problems associated with ever-shrinking System-on-Chip (SoC) process geometries. An analogue and mixed signal design engineer with over a decade of experience in low

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