Category Archives: IP Cores

5 Reasons Why In-Chip Monitoring is Here to Stay

April 20, 2017, anysilicon

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When the first car rolled off his production line in 1913, Henry Ford would have already envisioned just how prolific the automobile would become. However, would he have foreseen the extent to which monitors and sensors would become critical to the modern internal combustion engine?
 

 
The requirement

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Dolphin Integration announces the availability of the new generation 28 nm SpRAM generator

April 17, 2017, anysilicon

news

Launching any low-power SoC on a highly competitive market requires true differentiating factors. For IoT applications requiring ultra low-power solutions to extend battery life-time for wireless-connected devices, SoC architects optimize power modes by partitioning the SoC. This minimizes dynamic power in active modes, as well as power leakage in stand-by

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Silicon Creations Delivers 12.7G SERDES PMA for TSMC 40LP Process and PLL IP for TSMC 7nm Process

March 15, 2017, anysilicon

silicon creation

Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), today announced availability of several industry leading IPs for advanced TSMC processes including a 40LP 0.25Gb/s to 12.7Gb/s multiprotocol SerDes Physical Medium Attachment (PMA) and multiple 7nm PLL products. The PMA supports over 30 protocols including PCIe

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GreenWaves Technologies selects Dolphin Integration’s for the industry’s first IoT processor

March 13, 2017, anysilicon

dolphin office

 
Dolphin Integration, the leading Silicon IP provider for low-power SoC, announced today that it has been selected by GreenWaves Technologies to provide a consistent set of Silicon IPs for achieving the lowest power in sleep and active modes of GAP8, the industry’s first IoT processor. This set includes Dolphin

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ASIC-PLL Design Overview

February 08, 2017, anysilicon

pll

PLLs (phase-locked loops) are common analog circuits in SOCs (systems on chips). Almost all SOCs with a clock rate greater than 30 MHz use a PLL for frequency synthesis. However, a “one-size-fits-all” PLL does not exist. The devices have a range of frequency, power, area, performance, and functions. PLLs implemented

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Silicon IP reduces significantly power consumption of flash memories

February 06, 2017, anysilicon

lo power

Connected battery-based devices require always more computing power to run feature rich application programs while using the minimal energy to ensure the longest usage without recharge. As a result, fabless companies need to hunt down every “mA” to satisfy the low-power expectations of their SoC users.
 
Numerous System-on-Chips rely

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