Category Archives: IP Cores

Open-Silicon Expands Networking IP Portfolio to Address High-Bandwidth Ethernet Endpoint and Ethernet Transport Applications

November 15, 2017, anysilicon

Sprinter leaving starting blocks on the running track. Explosive

Open-Silicon today announced the availability of a comprehensive IP subsystem targeted at high-bandwidth networking applications. The subsystem expands on Open-Silicon’s existing high speed chip-to-chip Interlaken interface IP to include Ethernet Physical Coding Sublayer (PCS), Flex Ethernet (FlexE) and multi-channel multi-rate Forward Error Correction (FEC) IPs targeted for Ethernet endpoint and

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Semiconductor IP (Intellectual Property) Core – An Introduction

November 02, 2017, anysilicon

Examining a microchip

Sometimes called IP core or IP block, semiconductor intellectual property core is an integrated circuit or block, cell, or logic that is reusable that provides a design which is the intellectual property of its creator or party. The term itself comes from the source code copyright or licensing of the

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OmniPHY to Demonstrate Automotive Design Solutions at IEEE-SA Automotive Ethernet Technology Day

October 31, 2017, anysilicon

car

OmniPHY, Inc. OmniPHY Semiconductor, Inc. today announced it will be showcasing how it leverages automotive Ethernet technology to create robust automotive semiconductor IP solutions at the IEEE-SA Automotive Ethernet Technology Day forum. The event is being held on October 31 – November 2, 2017, at the San Jose McEnery Convention

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M31 Technology and Corigine have launched the world’s first USB-IF certified 28nm Superspeed+ USB 3.1 Gen 2 IP Solution

October 20, 2017, anysilicon

usb

M31 Technology Corporation, a global Silicon Intellectual Property (IP) boutique, today announced that Corigine’s USB 3.1 Gen 2 PC host and device controller intellectual property (IP) with M31 28nm PHY is certified by the USB Implementers Forum (USB-IF) and compliant with USB SuperSpeed+, the fastest USB speed standard.
 
USB

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Montage Technology Licenses Allegro DVT’s IP for Next Generation Set-Top Box Chips

October 19, 2017, anysilicon

news

Allegro DVT, a leader in video compliance streams and video codec semiconductor IP solutions, announced today that Montage Technology, a leading fabless semiconductor provider for smart home entertainment and data center markets, has licensed Allegro DVT’s AL-E100 multi-format H.264/AVC and H.265/HEVC encoder IP for integration into its next-generation set-top box

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Synopsys Announces Acquisition of Sidense Corporation

October 18, 2017, anysilicon

acquisition

Synopsys, Inc. (Nasdaq: SNPS) today announced that it has acquired Sidense Corporation, a leading provider of one-time programmable (OTP) non-volatile memory (NVM) for automotive, mobile, industrial and Internet of Things (IoT) applications. The acquisition complements Synopsys’ existing DesignWare®Multi-Time Programmable (MTP) NVM IP solution with OTP NVM IP in 16-bit to

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