October 28, 2016, anysilicon
I’d like to start by talking about the biggest misconception regarding RISC-V. Many of you who have heard about RISC-V likely believe it is an open-source processor … but it is not.
So what is it?
RISC-V is an open specification of an Instruction Set Architecture (ISA). That is,
October 24, 2016, anysilicon
Launching any SoC on a highly competitive market demands a differentiation for which Hisense was searching for an ultra low-power solution to extend battery life-time of wireless-connected devices. Designing such an integrated circuit introduces new challenges: silicon area, power consumption and BoM cost must be aggressively reduced, while dealing withRead More
October 11, 2016, anysilicon
Neuchatel, 11 October 2016 – CSEM, the Swiss Research and Technology Organization, today announced that they have licensed their IcyTRX™ silicon RF IP core to Danish hearing aid manufacturer Oticon.
Oticon has integrated IcyTRX™ IP core into their new chipset for the new Oticon Opn™ range of advanced wireless-enabled
September 09, 2016, anysilicon
Ridgetop Group, Inc. and Silicon Valley-based BaySand Inc., the leader in application configurable application specific integrated circuits (ASICs), today announced they will work cooperatively to develop a series of new applications to increase their existing mixed-signal intellectual property core (IP) portfolios.
Through a wide-ranging partnership, they also will offer
September 01, 2016, anysilicon
Sidense Corp., a leading developer of Non-Volatile Memory (NVM) One-Time Programmable (OTP) IP cores, today announced that it has demonstrated successful operation of its patented SHF 1T-OTP memory IP macros at TSMC’s 16FF+ and 16FFC process nodes.
Parametric measurements for both 16FF+ and 16FFC silicon were made during programmingRead More
August 24, 2016, anysilicon
IP-Maker, the NVMe expert startup, showcased its new SQL acceleration demo at Flash Memory Summit, reaching 200k+ transactions per minutes (TPM) on a low cost server, leading in a very efficient performance/cost/power consumption configuration.
“We used to highlight the low latency IOPS of our NVMe technology in the past