Category Archives: Verification
Evolution of the Test Bench
Nothing is permanent except change and need constantly guides innovation. Taking a holistic view with reference to a theme throws light on the evolution of the subject. In a pursuit to double the transistors periodically, the design representation has experienced a shift from transistors à gates à RTL and now to synthesizable models. As
Read MoreVerification IP : Build or Buy?
Consumerism of electronic products is driving the SoC companies to tape out multiple variants of products every year. Demand for faster, low power, more functionality and interoperability is forcing the industry to come up with standard solutions for different interfaces on the SoC. In past couple of years, tens of new protocols have
Read MoreThe 4th C in Verification
The 3C’s of verification i.e. Constraints, Checkers & Coverage have been playing an important role enabling faster verification closure. With growing complexity and shrinking market windows it is important to introduce the 4th C that can be a game changer in actually differentiating your product development life cycle. Interestingly the 4th C
Read MoreVerification IP : Changing landscape
For decades, EDA industry has been working out options to improve their offerings and ensure silicon success for the semiconductor industry. A few decades back, while the EDA giants were unknown, design automation was exercised individually in every organization developing a product. Gradually these tools moved out of the design
Read MoreChoosing the right VIP
In past few months, while interacting with customers, I came across a couple of cases where the VIP played a spoilsport. In one case, the IP & VIP were procured from the same vendor during the early phase of standard protocol evolution. One of the key USPs of the product was
Read MoreDebugging in System Verilog Constrained Random Verification
70 % of ASIC design goes in verification and 70 % of verification goes in debugging.
Planning for the debugging goes a long way. Feature by feature the way we architect the test bench pay some attention as to how will it be debugged. This strategy will pay back
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