January 21, 2015, anysilicon
Clock to an SoC is like blood to a human body. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the SoC. There are many terms which modern designers use in relation to the clock and while building the Clock Tree, the backend team carefully monitors these. Let’s have a look at them.
Consider a hierarchical design where we have multiple people working on multiple partitions or the sub-modules. So, the tool would be oblivious about the “top” or any logic outside the block. The block owner would define a clock at the port of the block (as shown below). And carry out the physical design activities. He would only see the Network Insertion Delay and can only model the Source Insertion Delay for the block.
Having discusses the latency, we have now focus our attention to another important clock parameter: The Skew.
We shall now take the meaning of terms: Global Skew and Local Skew.
In the next post we would discuss the implications of big clock latency on the timing.
This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India. To read more blogs from Naman, visit http://vlsi-soc.blogspot.in/
Image credit: ckaiserca