November 07, 2014, anysilicon
If your chip is late to market, it is costing you far more than you know.
Arteris conducted a survey of all its chip design customers to gain a more accurate grasp of the major concerns they have in their day-to-day operations and to gain a better understanding of what drives their decision making.
It is no surprise that time to market is one of the biggest concerns. The category that we call “Often late or slip” registered as a top design challenge to about 11 percent of the customers responding. Many of us here are quite surprised that this percentage isn’t higher.
Figure 1. Arteris recently conducted a survey of its customers top design concerns. ‘Often late or slip’ ranks as one of the key challenges. (Source: Arteris)
We think those who carefully consider the consequences of schedule slips have taken proactive steps to get to market on time or early. These same companies are taking market share in emerging, high-growth product categories, and they are getting design wins in time for the critical seasonal product cycles. That’s why these same companies place a priority on efficient execution. In our dealings with multiple customers, we’ve discovered companies that invest up-front in time to market wind up increasing their design starts. It’s no coincidence that many of these same companies also achieve volume leadership.
Power, performance and area concerns dominate most chip development and those costs are easy to quantify.
In our survey, 14 percent of our respondents said reaching design frequencies is a top design challenge and 13 percent said that low-power requirements were the most important.
When 11 percent of survey respondents indicate that debugging designs is a major challenge, or that complexity struggles represent 10 percent of top concerns, what this really indicatesis that time to market is the underlying cause.
Even when 10 percent say back end routing is a challenge, it’s clear that anything causing a chip to miss its introduction date adds to the cumulative anxiety.
Debugging designs, complexity and back-end routing can all derail time to market goals if chip design teams cannot address these challenges in an expeditious matter. Even other top concerns such as integration of third-party IP (10 percent) and the coordination of design teams (9 percent) speak to time to market.
But do chip companies really know the cost of being late? Or do they know how much pricing power they can gain by being early? We know that some companies really do understand how to calculate these costs and they are using this knowledge to execute more effectively.
Figure 2. Projecting the revenues over the lifetime of the SoC will be instrumental in calculating the costs of being late. (Graph: Arteris)
There is an easy way to calculate time to market factors and the potential loss of revenue if your chip is late. Look at a product sales window of 18 months to two years, for example, and determine how much revenue the product will generate over time. Research shows that products will reach peak revenue at the mid-point of the window. From that, companies can develop a growth curve for the introductory period and a downward slope after the market peak.
Using a formula based on proven economic research and actual industry experience, calculations show that in the case of a product with an 18-month long product sales window, companies will miss over 34 percent of product revenue if they are even three months late on introduction. To restate: If you are just one-sixth late, then you lose more than one-third of your potential revenue.
The formula for calculating the negative effects of shipping a product late to market is based on research conducted in academia, business schools and economics and it’s derived from commonly accepted principles about the technology adoption lifecycle. The concepts used to create this formula can also be used to estimate the added revenue potential of early arrival to market. It shows how companies can gain pricing power at the expense of the competition if they launch earlier than expected.
Arteris FlexNoC interconnect fabric IP is helping customers to accelerate time to market. It is helping companies integrate third-party IP at a faster rate and with greater ease. It is helping them to organize their global teams based on a hierarchy of design challenges. FlexNoC allows chip design teams greater flexibility to respond to engineering change orders. Compared to using obsolete hybrid bus or crossbar architectures for the SoC fabric, FlexNoC is far more effective in reducing the complexity of SoC designs. It also enables faster debugging and back end routing. Because of all these reasons, using Arteris FlexNoC SoC fabric IP reduces the probability that your chip’s schedule will slip, and increases the chances that you will be able to sell your product earlier than planned.
Any global design team that seeks to gain an advantage in a critical market should be well aware of the costs of being late to market. Factoring this important information in to chip planning will drive teams to place higher priority on getting their designs out in time to capture greater revenue.
This is a guest post by Kurt Shuler, Vice President of Marketing at Arteris. Click here to learn about Arteris products.