October 20, 2014, anysilicon
Yole Développement announces its Flip Chip Market and Technology Trends report. Yole Développement’s analysis updates the business status of the Flip-Chip market including data for TIM, underfills, substrates and Flip-Chip bonders. Discover fully updated 2010 – 2018 market forecast, detailed technology roadmap and bottom up approach, plus a strong focus on micro bumping for 3DIC & 2.5D.
Over the next five years, an incredible 3x wafer growth is expected for the Flip-Chip platform, which will reach 40M+ of 12’’eq wspy by 2018!
Despite its high 19% CAGR, Flip-chip is not new – in fact, it was first introduced by IBM over 30 years ago! As such, it would be easy to consider it an old, uninteresting, mature technology… but this is far from true! Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3DIC and 2.5D. Indeed, no matter what packaging technology you’re using, a bumping step is always required at the end! In 2012, bumping technologies accounted for 81% of the total installed capacity in the middle end area. That’s big. Really big. So big that it represents 14M+ 12’’eq wafers – and fab loading rates are high as well, especially for the Cu pillar platform (88%). Flip-Chip is also big on value: in 2012 it was a $20B market (making it the biggest market in the middle-end area), and Yole Développement expects it to continue growing at an 9% clip, ultimately reaching $35B by 2018!
Flip-Chip capacity is expected to grow over the next five years to meet large demand from three main areas:
1) CMOS 28nm IC, including new applications like APE and BB
2) The next generation of DDR Memory
3) 3DIC/2.5D interposer using micro-bumping.
Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.
In addition to traditional applications which have used Flip-Chip for a while now (laptop, desktop and their CPUs, GPUs & Chipsets – which are growing slowly but still represent significant production volumes for Flip-Chip), Yole Développement’s analyst expects to see strong demand from mobile & wireless (smartphones), consumer applications (tablets, smart TV, set top box), computing and high performance/ industrial applications such as network, servers, data centers and HPC.
The new “Flip-Chip packaged ICs” are expected to radically alter the market landscape with new specific motivations that will drive demand for wafer bumping. “In the context of 3D integration and the “More than Moore” approach, Flip-Chip is one of the key technology bricks and will help enable more sophisticated system on chip integration than ever before!”, says Lionel Cadix, Market & Technology Analyst, Advanced Packaging, at Yole Développement.
Flip-Chip is being reshaped by a new kind of demand that is hungry for Cu pillars and micro-bumps, which are on their way to becoming the new mainstream bumping metallurgy for die interconnection.
Meanwhile, Cu pillar is fast becoming the interconnect of choice for advanced CMOS (≤ 28nm), memory, and micro-bumping for 2.5D interposer and 3DIC
In addition to studying mainstream bumping technologies, this Yole Développement report focuses on Cu pillar bumping, which is becoming increasingly popular for a wide variety of applications. The massive adoption of Cu pillars is motivated by a combination of several drivers, including very fine pitch, no UBM needed, high Z standoff, etc.
Cu pillar Flip-Chip is expected to grow at a 35% CAGR between 2010-2018 in terms of wafer count. Production is already high at Intel, the #1 Flip-Chip producer – and by 2014, more than 50% of bumped wafers for Flip-Chip will be equipped with Cu pillars.
As early as 2013, micro-bumping for 2.5D & 3DIC, in conjunction with new applications like APE, DDR memory, etc., will boost Flip-Chip demand and create new challenges and new technological developments (see figure on the left). Today, Flip- Chip is available in a wide range of pitches to answer the specific needs of every application.
The ultimate evolution in bumping technologies will consist of directly bonding IC with copper pads. 3D integration of ICs using this bump-less Cu-Cu bonding is expected to provide an IC-to-IC connection density higher than 4 x 105 cm-2, making it suitable for future wafer-level 3D integration of IC in order to augment Moore’s Law scaling.
Taiwan is the #1 location for Flip-Chip bumping, announced Yole Développement.
The major OSATs are preparing to produce fcBGA based Cu pillar packages and won’t limit the reach of cu pillar bumping to fcCSP. This will allow every company involved in CPU, GPU Chipset, APE, BB, ASIC, FPGA and Memory to access Cu pillar Flip-Chip technology.
Cu pillar capacity is expected to grow rapidly over the 2010 – 2014 timeframe (31% CAGR), hitting ~ 9M wspy by 2014 and supporting the growing demand for micro-bumping and advanced CMOS IC bumping.
In the mutating middle-end area, CMOS foundries now propose wafer bumping services (TSMC, GLOBALFOUNDRIES, etc.), as opposed to bumping houses, which are dedicated to bumping operations (FCI, Nepes, etc.), and OSATs, which keep investing in advanced bumping technologies.
In 2012, OSATs owned 31% of installed capacity in ECD solder bumping and 22% of installed capacity in Cu pillar bumping. A full overview of 2012 installed capacities for all bumping platforms is provided in this report.
Concerning geography, Taiwan has the biggest overall bumping capacity (regardless of the metallurgy), with important capacity coming from foundries and OSAT factories. Taiwan currently leads the outsourcing “solder & copper” Flip-Chip wafer bumping market (see figure on the left). Flip-Chip market growth, spurred on by the emergence of the “middle-end” environment, has challenged traditional “IDM vs. fabless” supply chain possibilities more than ever before!
This is a guest post by Yole Développement that provides marketing, technology and strategy consulting.