Flip Chip Technology & Market Trends

October 04, 2015, anysilicon

Flip Chip technology is expected to reach $25 billion market value and wafer demand of 32 million (12”eq.wafers) in 2020, supported by the wider adoption of Cu pillar technology. That growth will be led by Moore’s law pushing beyond the 28nm node and ‘More than Moore’ evolution in next generation DDR and 3DICs.



Once more, the “More than Moore” market research and strategy consulting company Yole Développement (Yole) reaffirms its leadership in advanced packaging with its new technology & market analysis dedicated to Flip Chip technologies. This new analysis is entitled Flip Chip Technologies & Markets Trends (October 2015, Yole Développement).




Under this new report, Yole proposes a deep-added value analysis of the Flip Chip markets, players’ dynamics and key trends. The consulting company highlights the key market figures and presents future Flip Chip strategy evolution and opportunities. Strongly linked to the Cu pillar technology, Flip Chip solutions have been largely adopted towards the mobile-wireless, consumer and computing applications, including continuous growth in the LED and CMOS Image Sensor (CIS) segments.



“Flip Chip assembly technology provides various benefits such as high I/O counts, fine pitch interconnection, and superior electrical and thermal performance”, explains Thibault Buisson, Technology & Market Analyst, Advanced Packaging at Yole. And he adds: “This drives its application across specific segments.”





The maximum growth in flip-chip bumping capacity will come from Cu pillars, driven by the finer pitches, higher I/O counts, lithography nodes below 28nm, emergence of 2.5D/3D packaging, increased current density and thermal dissipation needs. In the meantime lead-free solder bumping is expected to grow at just 2% CAGR as OSATs and foundries converting their existing solder bumping lines to Cu pillar lines. With the scaling of the Flip Chip pitch, OSATs are presently pushing the envelope of C2 mass reflow bonding with capillary underfill to pitches as low as 50µm by formulating engineered materials and improving assembly processes. However, if the pitch reaches or falls below 40µm Thermo Compression Bonding (TCB) will be the key option because of its high placement accuracy.
TCB will be adopted first in high volume manufacturing by IDMs like Intel, who can bear the high cost of ownership, followed by memory suppliers for their next generation memories based on through-silicon via technology.
“Intel has recently qualified ASM’s high throughput TCB bonder for assembly of 14nm chips for their CPUs in applications such as data centers, servers, and high-end computing”, comments Santosh Kumar, Senior Technology & Market Analyst, Advanced Packaging at Yole. And he adds: “At Yole, we estimate Flip Chip bonders’ total market value will reach US$435 million in 2020, with a CAGR of 7%. Flip Chip bonders and underfill materials will become key in coming years.”  Therefore Yole’s technology & market analysis gives a complete and detailed analysis on TCB, advanced underfill materials, Flip Chip bonders and thermal interface materials.



This is a guest post by Yole Développement that provides marketing, technology and strategy consulting.