ASIC design comanies

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  • #4371 Reply
    Davide

    Is the number of ASIC design companies (world-wide) increasing or decreasing? is there any consolidation in this market?

    #4396 Reply
    sfhoover

    I am by no means an expert on market trends, but I can offer my personal perspective as an 18-year-veteran big-iron chip designer, and, recently, as the founder of an EDA startup. I’m writing this response mainly to help myself sort out in my own mind why many of my former colleagues are now looking for work. To the extent that you find it useful, read on. Sorry for the long answer, but mere statistics won’t help to draw useful conclusions.

    There is consolidation, but what I find to be more telling is the repartitioning of the design process. As the industry matures and as ASICs grow exponentially more complexity, the design process is partitioning into more decoupled layers. In particular, I’ll comment briefly on fabrication, and then I’ll talk about the influence of the IP ecosystem. I started my career with DEC in ’96 in the Alpha processor group. We had our own fab and did our own designs with our own tools, starting from RTL and schematics. It doesn’t work like this anymore, and we can extrapolate the changes over the years into the future.

    Layer 1, Fabrication:

    Fabs are becoming incredibly expensive, and, as AMD did with GlobalFoundries, large companies are separating fabrication from design. The expense of fabs requires consolidation and we have but a few foundries remaining. With the decoupling of fabrication and design, chip makers lose the ability to fine-tune their designs to the technology, and this is an acceptable trade-off. Design is now done at a higher level, as necessitated by complexity. It is increasingly up to tools to match the design to the technology (though we haven’t come as far in this department as one would hope). (Note that highly replicated structures, like memories and FPGAs, are a bit of an exception, as they still require device-level optimizations.)

    Layer 2, IP:

    Chip makers no longer start from RTL. As anyone participating in this forum knows, they start with IP and add in their own secret sauce, which is probably leveraged from a prior-generation design. As IP is the new space (in relative terms), that is where the industry is most dynamic. There are a relatively large number of new-ish IP providers. EDA and FPGA companies are focusing on IP as well as tools. They are acquiring smaller IP providers.

    So, with that in mind, let’s get back to the question. Is there a consolidation in ASIC design companies? I think there are factors in both directions, and, I’ll admit, I haven’t researched the numbers.

    I believe consolidation is natural in a maturing industry. There is also an impact of shrinking fabrication technology. As more logic fits on a single chip there is an integration of components and this can correspond to the merging of companies. We saw this with AMDs acquisition of ATI. We saw it again with the acquisition by Intel of Altera, where Intel will look to integrate FPGA logic on-die with CPUs and other components.

    But, I believe the most significant changes we are seeing today are fallout of the migration to SoC/IP design methodologies. The Intel’s and IBMs of the world have been growing their design teams for years to scale with increasing complexity. They have in-house tools that once offered competitive advantage. Large, experienced design teams working on the most aggressive designs, using their own favorite tools, are resistant to constraining themselves with off-the-shelf IP. But off-the-shelf IP is now competitive, and the scale of monolithic design teams is impractical. Smaller SoC design teams get better results, faster, and have figured out the better formula for today’s constraints. Now, the big boys have admitted defeat and need to reset to this leaner model, and they have a lot to catch up on and a lot of baggage to offload to get there.

    To transition a monolithic design team to an IP integration team, the breadth and depth of old-school design experience is no longer as valuable. As a result, I’m currently watching many of my former colleagues from Intel struggle to find new jobs as Intel hires cheaper college grads and overseas engineers.

    Do I think things will rebound? Somewhat. I do believe we are seeing a correction, and growth is still the underlying nature of the industry. But I expect the renewed growth to be slow. IP is becoming commoditized. Long-term, I expect a slowly emerging open source hardware ecosystem to compete with paying IP design jobs. Fortunately, complexity grows exponentially, and that will keep us employed.

    For those looking for design work today, I can only suggest refreshing your skills. Learn IP integration tools; learn the latest verification methodologies. Perhaps look at what you were doing, step up one level of abstraction, and focus there. Personally, I decided it was time for better mechanisms to deal with complexity, and changed my focus to EDA. Whatever you do, please do not rely solely on your RTL expertise! For logic design, the challenge is predicting which new technology will stick. HLS/System C is the most obvious choice, but not necessarily the best. My gamble is Transaction-Level Verilog, and there are other interesting possibilities as well. Whatever you choose it’s important to be able to convince a prospective employer that you bring a unique skillset to the table.

    But, back to the question, I think the big guys are shrinking and consolidating, but I also think we have been seeing for several years that there is more opportunity lately for startups to compete. Let’s hope so, I’m one of them.

    My 2c for what they are worth. I’ll learn from your criticism. Fire away.

    Steve Hoover
    Redwood EDA

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