we are running big ASIC projects in high volume and having an internal debate, perhaps one of you could share his experience and thoughts, would you recommend producing corner wafers (split lot), how many wafers? is it a good investment?
Corner/Spilt lot is usually used for the following:
1. Device characterization (both on ATE and System).
2. Device reliability qualification (mainly in HTOL).
3. Test program robustness.
It is a good practice to produce a split lot for any new product or product families.
Usually this is 12 wafer lot, where every 2 wafers are processed to a different corner (Slow/Fast/Typical for both Core and IO).
You can also ask to vary additional parameters if you know that your design is sensitive to them (e.g.: specific capacitance).
Yes! The moment you state high volume it is a critical to optimize the wafer production towards an optimal yield.
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