I’ve been using FPGA for 3 year , why designing a custom chip is so costly? are they any cost that I don’t foresee? BigMike
Hey FPGA guy,
I can see where you are coming from. Making the 1st ASIC could be an expensive process that requires design & tools. But the 2nd, 3rd etc ASICs in the production will always be cheaper than an FPGA.
This means that for every high volume (and sometimes even low volume) ASIC project will have a good ROI compared to an ASIC.
I can count several reasons for explaining why ASIC NRE cost is so extensive:
1. design, verification and layout hours spent
2. IP core cost
3. Tools: maskset, package, test solutions
Anything I missed?
you’re right. For next generation of ASIC chip, the cost will go lower.
Production setup, Production Ramp-up, Production optimization (Yield optimization)
Device qualification (HTOL, ESD, LU, HTSL, …)
Comparing FPGA with ASIC the ROI is solely relying on
1. reducing the overhead and thereby reduced the die size -> reduced die cost.
2. Business model – reduce the margins in the supply chain e.g. standard device 60% GM to ASIC 40%, to COT mode …
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