My Golden Rule for Chip Production Testing

March 10, 2014, anysilicon

Chip production testing is probably the most underestimated task by ASIC development engineers. And yet, testing is an essential step with a direct impact on final chip cost.


Let’s start with the basics. Testing of chips is necessary because the chip manufacturing process cannot provide 100% yield. Silicon foundries and assembly houses are producing ICs but some of them consist of defects and failures, and these chips need to be screened. Therefore, every chip has to be tested before it is shipped out to the market.


Chip testing has two goals:

(1) obtain maximum test coverage so you deliver high quality ICs and

(2) keep testing time to minimum to keep costs down.


Of course, meeting these two goals simultaneously is not possible and like in real life, testing strategy involves tradeoffs. A quick example: the duration of test is directly linked to test coverage – the longer the test – the better test coverage. But if test duration increases, so does the cost per chip.


In semiconductor testing I follow a very simple guideline that I’d like to share with you. It’s my golden rule for testing strategy that worked for most projects I worked on. It combines ROI, quality, politics and time to market and most of all – it makes engineers, salespeople and marketing people happy.


Here it goes (and it’s quite complicated, so read carefully):


The chip production volume is the best indication for defining the chip test strategy. For high volume runners, I plan high NRE investment. For low volume projects – I plan low NRE investment. For medium volume, I plan medium NRE investment.


If production quantity over lifetime is high, your company can benefit a lot if you create a robust test solution that is optimized for minimum test time.  The following are a few ideas I apply for high volume runners:


Try to reduce test duration using any of the following methods:

  • Add test blocks inside the chip. For example: BIST- built it self-test, different internal loopbacks to test transmitters and receivers, internal memory tests, etc.

  • Add hardware on the test board (load board) to perform very dedicated testing to speed up the test process. This can be done by an FPGA for example.

  • Design multi-site testing (testing ICs simultaneously). With today’s advanced semiconductor testers some companies are testing 32 ICs in one go.


When it comes to the hardware that physically connects the chip or wafer to the tester — don’t settle on low quality products.  Socket or needles are extremely important. Try to get the best quality products you can buy. Why? Because if your socket wears out quickly, the tester will start losing contact with the chip-under-test, and will start reporting false failures. This means you’ll be throwing out good devices.


The same approach is valid for wafer sort. If you buy low quality needles, sooner or later the needles contact to the wafer will not be so solid, which will result in labeling some dies as faulty.


You can easily draw the conclusion for other scenarios (low volume, mid-volume) based on these examples. Or maybe you have some other ideas you can share.


The semiconductor test development companies listed on AnySilicon’s directory can help you with your next IC testing project.

  • Michael Fox

    Good rule.

    I’d like to ask about FPGA on loadboard. I’ve developed some for FPGAs and it’s a big undertaking. I’ve never used it for test as it seems a lot more work than I could justify. Is there some platform IP or tools that target testing which makes the undertaking feasible?