August 01, 2016, anysilicon
According to Gartner, the total average IC design cost for a 14nm chip is about $80 million, compared to $30 million for a 28nm planar device. Whilst many vendors will remain at 28nm, the ‘big guys’ have forged ahead with migrating to lower technology nodes. At the leading edge, R&D teams are now wrestling with 7nm. In this blog we will look in detail at the realities and challenges facing designers when moving from a 28nm to a 16/14nm technology node, and the impact on the RTL2GDSII physical implementation flow.
The features in nodes below 20nm are so small that it’s no longer possible to mitigate the effects of diffraction. This is caused by the relatively large light wavelengths (193nm) used during the lithography steps. For this reason it’s necessary to adopt a double patterning masking technique. This allows for the required increase in accuracy necessary to produce the small features, whilst retaining the same lithography techniques used in larger nodes (> 30nm). Advanced lithography techniques, such as Extreme UV (EUV) with a wavelength of 13.5nm, are not yet ready for mass production.
The effect of DP on the Back End flow will be,
There will also be a side effect which is caused by using two masks. The tolerance of the alignment between these masks needs to be accounted for in extraction and static time analysis.
The effect of DP on production is the added cost and time of producing and using twice as many mask/reticles (compared to a 28nm process not using DP).
As the technology node continues to get smaller, the layouts become increasingly dense and a single exposure will not work. The LELE (Litho-Etch-Litho-Etch) DP technique allows the dense layouts to be split into two lower-density layout masks. The foundry then uses two separate exposure processes to form two coarser patterns, which are superimposed to form a single, finer image on the actual wafer.
Figure 1: LELE DP layout decomposition (Mentor)
The LELE DP technique is the most commonly used, but there are also two other schemes– LFLE (Litho-Freeze-Litho-Etch) and SADP (Self-Aligned Double Patterning). Further information about them is provided in the links below.
Planar FETs are not viable at the 16/14nm nodes, as they have poor electrostatic control due to SCE.
In simplistic terms SCE means that small planar FETs (<20nm) suffer from high leakage current and poor gate control (i.e. high off current and it’s hard to turn them off). These effects are caused by DIBL (Drain Induced Barrier Lowering) and deep sub channel current flow that cannot be controlled (see figure 2) as it is too far from the gate.
Figure 2: Bulk CMOS transistor (EDN Network) Figure 3: size shrink drain current vs gate voltage
Figure 3 shows how size shrink lowers VT but also increases the off current, resulting in a FET that cannot be turned off.
Drain-Induced Barrier Lowering or DIBL is a short-channel effect in MOSFETS, referring to a reduction of the threshold voltage of the transistor as the drain voltage increases. In a classic field-effect transistor with a long channel, the threshold voltage is independent of the drain voltage. This is because the bottleneck in the channel formation is so far away from the drain contact that it remains electrostatically shielded from it. ( This is true regardless of the drain voltage). In short-channel devices this is no longer true. The drain is close enough to gate the channel, and so a high drain voltage can open the bottleneck and turn on the transistor prematurely.
SCE is present in <60nm nodes but becomes unmanageable in <20nm nodes. For this reason it is necessary to use a different process at the 16/14nm nodes. The semiconductor industry seems to be splitting into two camps to solve this problem. One using FinFETs and the other using FD-SOI technology.
Whilst FinFETs and SOI achieve the same end goal of eliminating SCE, their respective manufacturing processes are very different.
Compared to planar FETs, FinFETs are a radical redesign and therefore the manufacturing process is very different and requires complete re-tooling. The process for SOI is similar to planar FETs and only requires two additional process steps. That said, FinFETs seem to be the most popular choice for 16/14nm nodes. It is stated that both FinFET and SOI technologies are scalable down to the 7nm node.
The picture below shows the difference in structure of a bulk planar FET compared to a FinFET. The FinFET is effectively like a planar FET that has been rotated 90 degrees so that it stands up out of the substrate. This has two main advantages: 1) The channel depth is now defined by the width of the Fin and so no deep channel currents can flow. 2) The gate contact is now on 3 sides of the channel giving improved gate control.
Note: The diagram below is drawn from a different perspective to normal FET diagrams (the source is at the front and the drain is at the rear, normally the source is on the left and the drain is on the right)
Figure 4: Planar FET vs. FinFET (Synopsys)
Intel calls their FinFET a TriGate, and the benefits are:
FinFET further reading
Introduction to FinFETs. (in depth description. duration 25 mins )
The diagram below shows the difference in structure of a bulk planar FET compared to an FD-SOI FET. The FD-SOI FET is very similar to the bulk device but has an extra layer of Insulator (BOX in the diagram). This has the advantage that the channel depth is defined and the deep channel currents can no longer flow. The gate control area is the same as a normal bulk FET i.e. one sided, but because the channel is now a controlled depth (shallow) it is fully depleted and so control of the gate remains even with short gate length at 14/16nm node. Another advantage is that back biasing techniques (as previously used on bulk planar FETs) are still possible and in fact are even more useful as the layer of insulator removes the unwanted effects of back biasing, allowing even more control of gate parametrics.
Further SOI reading
SOI structure (animated description. duration 8 minutes)
Miller Effect and long tail effect
Process nodes at 20nm and below introduce wave form distortions rarely observed before. The Miller effect is stronger due to the increase of the capacitance as the technology node scales down.
Another issues is the increase of wire resistance, which causes long tail effects that impact on the STA delay accuracy.
Images taken from Synopsys:
Figure 7: Long Tail Effect (Synopsys)
50X difference in metal layer resistance
As we are going to 20nm, layer stacks become very heterogeneous, RC varies as much as 50x between layers, which is leading to a significant timing variation due to layer assignment.
Figure 8: Metal layer stack variation across process nodes (EE Times)
Double patterning impacts every part of the IC design phase, from standard cell development to placement, routing, extraction, and physical verification, and there are certain requirements that the designer should know:
Circuit performance is more dominated by interconnect Rs and Cs
Significant crosstalk impact on circuit performance
The move to FinFET brings new challenges to the extraction tools, as the transistors have a variety of 3D fin shapes, that create 3D capacitance.
Double patterning has a variation which needs to be taken into account by the extraction tools.
Increased metal resistance at emerging nodes causes transition tails to increase (Long tail). When the input waveform deviates from the characterization waveform, an inaccurate delay is calculated – solution by PrimeTime: PrimeTime advanced waveform propagation (AWP) reproduces accurate SPICE response.(Synopsys)
Unlike the move to previous nodes, for example moving from 40nm to 28nm, moving to 16nm isn’t only a matter of making the transistor smaller. The move forces us to use both
The impact on the Back End (BE) is that we are using more sets of tools/features to get the job done, and it takes longer to signoff a design (both tool runtime and engineers’ work time).
This is a guest post by Sondrel, which is an IC design services consultancy company.