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An Introduction to On-Chip Variation (OCV)

February 28, 2017, anysilicon

On Chip Variation (OCV) is an increasing problem that starts at 130nm and its effects are increasing with smaller process nodes. And On-Chip Variation (OCV) is one of them, specifically for Static Timing Analysis.

 

The first task is to find all possible sources variation, and find out how these can affect a delay of a cell and hence, timing.

 

In this article I will focus on the various sources of on chip variation:

 

 

Etching

 

Let’s look into the below layout of an inverter (which also shows the Width (W) and Length (L) parameters of an inverter)

 

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAANoAAAAJDM5YjczMWFlLTYwNDYtNDU3OS1hMGIyLTI0ZjYzZmZkNWE2NA.png

 

….and, a chain of inverters (this is mostly the case of clock path, be with me for upcoming posts and I will exactly let you know, why OCV is mainly applied on clock paths, 50% should be clear from the term “chain of inverters”)

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAANLAAAAJDNjNjc5ODJjLTdkNjQtNDViMy04ZjM3LWM0NTk3MzgyMDJjOQ.png

 

We use photo-lithography fabrication technique to build the inverters on Silicon wafer, and this is a non-ideal process, where the edges will not exactly be straight lines, but there will be disturbances. And why so, because the above technique needs photo-masks which are created using etching, which is again non-ideal. Below is how the ideal mask and real mask look like

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAOKAAAAJDZhMDlkNjFmLTAyN2EtNDk3MS1iNTYxLWQ5MjgwMjY3NDIyOQ.png

 

Now these variations on the sides, is also dependent on what logic cell is present on either sides of this inverter, if its surrounded by chain of inverters on either sides, the variation on the sides will be less as the process parameters to build mask for a chain of similar size inverter, is almost the same. But, if the inverters are surrounded by other gates, like flip-flops, then the variation will be more.

 

With that said, the below inverters in the middle will have a similar and less variations

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAJ_AAAAJGE5MzQ5YTNmLTg3NmEtNDU1Yy05YmM2LTNiMzUyODA5OTU4Yg.png

 

and the inverters on the boundaries will have different and more variations. (observe the difference in actual mask, in above image) And guess what…. this directly impacts the drain current below, as it is proportional to (W/L) ratio

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAJEAAAAJDJkZTZmMzU0LWNkZGItNGVmZi1iZjVhLWQwOWFjMGQ2ZTY4Nw.png

 

These OCV values he should be used it in STA analysis and see its (+ve or -ve) impact.

As we were identifying sources of variations, and below is the second one

 

Oxide Thickness

 

Let’s go back to the inverter layout and look which part are we talking about. Here, we are talking about gate oxide thickness variation

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAALPAAAAJDc0Mzc1Mzk1LTdjNGMtNDdiOC1iMDI1LWIxMmYwOTQ3NTg2Yw.png

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAIsAAAAJGI3MTdkNDU3LTI5YWQtNGEwOS05MmVmLTA3ZDAxNmZjN2YzMQ.png

 

If we go by ideal fabrication process, below is what you will achieve, a perfectly cubic shape (below is the 2D image, so it looks rectangle) oxide layer, and perfectly deposited metal gate or polysilicon gate

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAALYAAAAJGU4YTY4ZmU1LTQ2ODQtNGFiZS1iZWVjLTY2ZDhlNzE0YWMyMg.png

 

But, if we go by actual oxidation process, it’s very difficult or almost impossible to achieve the above perfect oxide thickness.

Below is what you will actually get

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAJeAAAAJDhmZDFjN2EwLTQyZDktNGExYi05OTU4LThmMWUyNDQwM2ExYQ.png

 

So, what’s wrong having above oxide thickness. Again, it’s the drain current (which is a function of oxide thickness, shown in below image) that will get varied for the complete chain of inverter, especially, the ones on the sides. The variations in middle inverters will still be uniform.

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAANJAAAAJDI0YTBhNjZmLWMxYTEtNGFiNy05NDk4LWY2MWRkNGJjMTUxNQ.png

 

Imagine a chain of, as long as, 40 inverters or buffers…. the variation is HUGE. And this needs to be accounted for, in STA.

 

So the challenge is, how to we find the range and effectively model it in STA.

 

The below image models “low-to-high waveform condition” at input of CMOS inverter, in terms of resistances and capacitances. So, overall, it’s the RC time constant that actually decides the delay of a cell

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAANwAAAAJGI4MjM4MzZjLWVkMTktNGE0NS1iODljLTNiNjYzMTZkNTg3OA.png

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAJfAAAAJGJjNzBhNThjLTY2MmUtNDQ5MC1hN2FhLTNiN2Q0MWZiZjJkMQ.png

 

With above, we can safely say, the propagation delay tPD is a function of ‘R’

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAANhAAAAJGQ2NTNjYjgzLWM0MzktNGZjMC1hYmJhLWE1Y2JmNTQwZTVlZA.png

 

We see variation in drain current ‘Id’ due to variation in ‘W/L’ and ‘oxide thickness’ variations, and above we see, how propagation delay is function of ‘R’. The question is now, what next? If I am, somehow, able to prove, that drain current ‘Id’ strongly depends on ‘R’, then I can directly relate (W/L) and oxide thickness variation to ‘R’, and below images will exactly do that

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAN2AAAAJGZjMWI3OTdhLTZiNGItNGU3YS1iZTY0LTdkZjAwZmI5Yzc5OQ.png

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAJgAAAAJDU1Y2QyYmU0LWIyNGItNGY4Ni04ZTk1LWRmZDljMjU0YmMzZQ.png

 

Hence, every inverter in the below chain, will have delay which is different than the immediate next one, something like below

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAAKGAAAAJGNjYjg1MGMzLTMzMDQtNDJjZC04OGYwLTk4NmNkYmJkNzM4Yg.png

 

 

If we plot a Gaussian Curve with delays on x-axis and no. of inverters on y-axis, it will give us a clue, about the peak variation in inverter delays, the minimum and maximum variation in inverter delays like below

 

 

https://media.licdn.com/mpr/mpr/shrinknp_800_800/AAEAAQAAAAAAAALbAAAAJGQ2N2JjN2IzLTVjYjYtNDRhYi05ZWI0LTU2ZTdkMzhkMDA2OA.png

 

 

Now, we know the percentage variation in delays of inverter compared to ‘100ps’, because that’s where the inverter delay (with used ‘W/L’ ratio) is expected to be, and most number of inverters on chip with that ‘W/L’ ratio have a delay of 100ps.

 

OCV variation is +8% and -9% and one of them will be used for launch and other for capture in setup/hold timing calculations. For eg. for setup calculation, the launch clock will have OCV of +8% and capture clock path will have OCV of -9%. That means, if the original clock cell delay is ‘x’ in launch clock, with OCV into account, the same clock cell delay will be (‘x’ + 0.08x). This calculation in setup takes into account the On-Chip Variation, and that’s where the name comes from, as shown in above image.

 

 

This is a guest post by Kunal Ghosh with http://www.vlsisystemdesign.com/

  • Kev

    Need to model variation in functional verification? Try this –

    http://www.v-ms.com/ICCAD-2014.pdf

    – that’ll catch CDC errors, as well as providing time and power closure, and give yield estimates with your existing test-benches.