February 04, 2013, anysilicon
HTOL (High Temperature Operating Life) is a stress test defined by JEDEC to define the reliability of IC products, and is an essential part of chip qualification tests. This post provides a high-level overview of HTOL. Obviously you should refer to the standard if you intend performing testing.
To predict reliability and operating life of IC products, JEDEC has defined a stress test that exposes the IC to extreme temperature conditions. Test results are then used to predict the long term failure rate of the IC.
An HTOL test is performed in an oven with 125C degrees, while the ICs are activated with dynamic signals and the VCC pins with max voltage. The details are specified in the following table.
|JEDEC Standard||JESD22-108, JESDS85|
|No. of Lots||3|
|No. Devices per Lot||77|
|Accept criteria||0 fails|
After the HTOL stress test is completed the ICs must go through electrical screening to determine how many devices passed or failed the stress test. The JEDEC requirements define zero failures as an acceptable criterion, with test results defined in terms of FITs (failures in time). One FIT symbolizes one failure in 109 device hours.
To perform the HTOL test, all ICs must be in an oven, ideally placed in sockets and located on a PCB. Both sockets and burn-in-board must be able to withstand the high temperature during the test.
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