Negative Delays aren’t so Negative after all !

July 18, 2017, anysilicon

You read the term “negative delay” and your engineer mind goes racing creating science fictions – time machine, time generator, non-causal machine and so on. Here are the answers – no, you can’t turn circuits with negative delays into a time-machine, you can’t go back in time, you can’t even increase frequency of a chip. So calm your nerves and allow us to debunk myths behind negative delays. In this article- we’ll define delays, explain negative delays and sources thereof.


What is propagation delay?


Signal propagation delay is, nothing, but measurement of time between two signal. These two signals could be anywhere in the circuit, i.e. input and output pins of a cell, two nodes of an RC tree or start and end point of a time path.


In the context of a cell or circuit, change in input pins state could cause a change in output pin. Signal is said to have reached a point of no return in the transition, once it crosses a certain threshold. These thresholds are predetermined for the circuit. They could be different for rise and fall transition, input and output pin of a circuit or standard cell. These are typically set at 50 percent of the rail voltage (difference between power and ground voltages) of a signal. In this context rise or fall (propagation) delay of a circuit/cell is defined as


propagation delay = 50% threshold of output transition – 50% threshold of input transition


Under normal circumstances, propagation delay of a circuit/cell is positive, i.e. input signal reaches its 50% threshold before output signal reaches its 50% threshold.


But, how can delay go negative?

Sometimes cell (typically with strong drive strength) may exhibit negative propagation delay. This does not mean that standard cell’s input and output have non-causal relationship. This is simply a manifestation of choice of delay threshold points. Picture below shows an example of negative delay of a simple inverter, when falling input A transition causes a rising transition at output Y.

Negative delay of standard cell (inverter circuit)

It is easy to see in the picture that input signal A starts to fall at 0ps, whereas output signal does not move from low voltage (ground, VSS or 0.0V) until 235ps. This reinforces our earlier statement about causality of these two transition. Given rail voltage of 1.2 volt, delay threshold point of 50% translates in to a 0.6V of theshold. Notice that input reaches 0.6 Volt (50 percent threshold of input rail voltage) at 500ps, whereas output is able to reach this threshold 0.6 Volt (50 percent threshold of output rail voltage) at 467ps.


Using propation delay equation defined above,

propagation delay = 467ps – 500ps = -33ps

And there, we witness negative delay for this transition.



So, what causes negative delays?


There could be many reasons for negative propagation delay of a circuit/cell, some of them are given below.

  • Poorly designed circuits,
  • Poor choice of delay thresholds,
  • Cell/circuit operating beyond their designed specifications,
  • Cell/circuit’s asymmetric PMOS/NMOS drive strength operating under slow input transition time and used to drive small load.




In this article, we defined propagation delay. We, also, saw how a propagation delay could be negative and why does it not represent non-causal relationship between input and output. In the end, we outlined few probable causes of negative delays.



This a guest post by Paripath, find more information here: http://www.paripath.com/