Optimized ASICs for Medical Applications

June 07, 2017, anysilicon

A few years ago Derek Hunt offered some insight into the benefits of CMOS semiconductor technology in the miniaturization of medical devices. CMOS has been around for decades and aside from the size benefits which will be discussed shortly, the technology also brings significant cost savings and performance improvements to the medical world. Readers who are currently engaged in the design of medical electronics already recognize this. It’s actually difficult to design such products today without incorporating CMOS devices. And because medical devices often contain many analog components, there remains one critical decision point designers must address and that is whether to design with standard off-the-shelf standard analog products or engage with a semiconductor company to produce a custom analog chip for the application. I know what you’re thinking, “Not for me. Way too expensive.” But before you click off to another web site, let me give you a spoiler alert; the custom chip is by far the better approach. Let’s explore why.


  1. Annual mega-volumes are not necessary…unless you try dealing with a mega-chip company. Look around. Silicon Valley and other analog centric geographies like Austin, Boston, Dallas and Phoenix, host a growing number of specialized analog IC companies that engage in the design and production of analog Application Specific Integrated Circuits (ASICs). These smaller, more nimble firms cater to serving quality custom products at extraordinarily competitive prices, to the medical, industrial and automotive markets.
  2. NRE and tooling costs range from zero to a few hundred thousand dollars. Yes, you read that right… zero. Some Analog ASIC companies offer 100% rebates over the lifetime of the IC’s usage. Others use design techniques called tile arrays that accommodate implementation of simple designs on prefabricated silicon where the preexisting analog functions on the silicon are interconnected per the customer’s request. Others use cell libraries to reduce the design time, as well as cost, to create sub-critical performance but cost effective products.
  3. Development times are short. Turnaround can vary from a several weeks (tile arrays) to six to nine months for silicon evaluation of a full ASIC.
  4. Your design is protected from the Asian product pirates. What could be worse that having a replica of your product hit the market within months of your release? Products using off-the-shelf analog ICs can be copied immediately. With an ASIC, there is no datasheet in the public domain to alert your competitors as to how your product works. And the chip cannot be sold to anyone but you.
  5. Size matters. As sensors and signal condition and calibration circuits coalesce, your products are getting smaller. If your PCB is populated with numerous analog chips, it is also burdened by the many resistors and capacitors needed to compensate, couple or bypass signals. Nothing shrinks the size of your design like analog ASICs because most if not all these passives can be integrated or eliminated with a chip that is designed to do exactly what your need and nothing more. If you’re in doubt, try putting several standard products in the tip of a distal and running it up the femoral artery.
  6. Costs plummet. Approximately 60% of the $43B global analog IC market is ASIC. If you are using a compilation of standard off-the-shelf analog ICs in your design, you’re among the minority. If your volumes are quite small, it’s the right approach. But if your volumes are a few tens of thousands or greater then you should investigate the cost savings available to you through analog integration.
  7. Reliability increases. Product reliability is a function of the mean time between failure (MTBF) of any component and the number of components in your design. Because analog integration gobbles up more than just the sum of the number of analog ICs in the design, reliability improves disproportionately.
  8. Product obsolescence becomes a non-issue. Semiconductor companies discontinue products at their convenience, not yours. Using standard off-the-shelf analog ICs puts your design at risk of the sudden and unexpected notification that one or more of the devices you are using may no longer be available in the near future. With an ASIC design, as the only customer, you are in control of the longevity of the chip.


The many reasons to consider analog ASICs in medical applications are striking and admittedly, for the uninitiated, the idea can be overwhelming. For example, analog ASICs can greatly simplify sensor conditioning and calibration because of the flexibility of their form factor. Standard ICs are typically square silicon chips and communicate via long thin wires to a sensor that has been inserted into an artery. A custom ASIC design can have a large aspect ratio, perhaps 5 or 10 to 1, making it long and narrow, allowing it to fit inside the catheter and accompany the sensor element to the signal source, reducing or eliminating the potential for noise pickup by the instrument.


Analog ASIC companies are professionals at developing and maintaining close relationships with their customers. These are not typical buyer/seller relationships that can sometimes become adversarial. Developing a custom chip requires deep mutual understanding of the customer’s application and the capabilities of the ASIC supplier.


There are several elements you need to explore internally before engaging an analog ASIC semiconductor company to design and produce a custom chip for you. Once you are comfortable with this internal analysis, you can then explore possible suppliers. Let’s take a moment and examine some of the more important aspects.



  1. Identify your existing BOM costs. When asked, most customers simply get a list of components from their purchasing department along with the price they currently pay for them. Less obvious are the ‘other’ costs associated with these components. For example: purchasing costs, inventory costs, manufacturing costs including labor costs (whether human or machine), cost per square inch of the PCB, or cost of lost production when there is an availability or quality problem from a supplier.
  2. Identify availability of your resources…to manage the transition from using many standard chips to a single ASIC. Someone needs to be the focal point when dealing with the ASIC company to field technical questions and answers, help define the electrical specification for the ASIC, conduct progress reviews and design reviews, manage the production change over.
  3. Understand the longevity and cumulative volume expectations of your product. Analog Applications typically have long lifespans and can easily support and justify the transition to an ASIC chip. Many industrial and medical applications can last 10 years or longer.
  4. Mitigate risks. Do not separate ASIC design from ASIC production. The design team needs to manage the production. Even if you have contracted digital ASICs before and have managed the production and/or test yourself, if there is one takeaway from this paper it is that Analog is different. Parametric performance in the digital world is almost a no-brainer. Every function that connects to another function has a well-defined interface. It’s either a logic 1 or a logic 0 and each of these has a well-defined min and max limit. This is not the case with Analog. Analog design requires that thousands, possibly tens or hundreds of thousands, of device interconnects on the chip match exactly. Another way of looking at it is to recall that Analog behavior is described by a set of mathematical equations; digital by Boolean relations. Designing analog functions on digital silicon processes, as many mixed signal ASIC companies do, is like framing a house with balsa wood; the more you add, the shakier it gets. The design skills and production processes needed for analog are very different. The odds are very much against you that you have in house or can hire a capable team to execute this flawlessly. Seek out a full service analog ASIC supplier that manages design and production and test of the ICs for you. Developing an analog test system can be as complicated, if not more so, than developing the analog IC. Make sure you contract all of it as a single project with one supplier responsible for everything.


When you think you’re ready to engage with an Analog ASIC supplier, consider the following:


  1. The cost of the NRE and Tooling can vary greatly. Variables include the design complexity (man hours required to design and layout the chip), mask costs (determined primarily by the lithography of the wafer process; 0.18um, 0.35um, 0.5um, etc.), wafer costs (determined in part by the wafer size (150mm, 200mm, etc.), and by special needs (number of layers, SOI, cavity etch for sensors, etc.). Your Analog ASIC supplier will review with you any options and tradeoffs you may wish to consider that might minimize any of these costs.
  2. NRE and Tooling Rebates. Ask your Analog ASIC supplier if they offer a rebate program for the up-front costs associated with developing the chip. These are implemented during the early production lifetime of the product, and are a means of further equalizing the cost of an ASIC with that of a standard product. It essentially has the effect of making the front end costs appear as a loan that gets paid back as production is consumed rather than treating it as a sunk cost.
  3. Be sure your supplier has longevity. It takes a lot of experience and a lot of capital to maintain and grow a semiconductor company. Don’t be duped into thinking that a handsome website qualifies as a viable contender. More importantly, ensure that the design team themselves all have long rich histories of analog IC design. The simple hard truth is that colleges and universities are not producing analog designers. That skill comes from hands on experience, working side by side the legends of the industry, not from books and not from doing cell based mixed signal work. There’s a big difference between knowing how to use an instrumentation amplifier or an A/D converter and knowing how to design one in silicon. If your chosen design team doesn’t have gray hair, you may be in for an unpleasant surprise.


A couple of additional side notes to file away in your memory;


  1. When it comes to Analog, there are no shortcuts. If you insist on beating up your chosen supplier to quote shorter and shorter development times, it may backfire on you. Although delivery of first samples sometimes occurs in as little six to eight months, realistically you should expect it to be closer to ten to twelve months and even longer for very complicated designs. Individual quotes will vary.
  2. Think about your IP. If your design is simply an amalgamation of off the shelf standard products with no inherent invention in the design, you may not care. But if the chip will be containing your own proprietary IP, check very carefully as to where your chip will be designed. Yes, engineers in the US and EU may be more costly, but what are the costs to you and your business if your design is stolen? Have you ever wondered how products like the new Apple watch become available for sale on Alibaba before being released by Apple? The same holds true for wafer fabrication. If you are at all concerned, insist that the product be fabricated where the Rules of International Law apply.
  3. Don’t be penny-wise and pound-foolish. When having an Analog ASIC made for you, be very thorough about whom you select to design and build it. The cheapest solution may not be the best solution.


About the author:

Bob Frostholm is Vice President of Marketing & Sales at JVD Semiconductors, (San Jose, CA.)

Bob has held Marketing, Sales and CEO roles at established and startup Analog Semiconductor Companies for more than 40 years. Bob was one of the original marketers behind the ubiquitous 555 timer chip. After 12 years with Signetics-Phillips, Fairchild and National Semiconductor, he co-founded his first startup in 1984, Scottish based Integrated Power, which was sold to Seagate in 1987. He subsequently joined Sprague’s semiconductor operations in Massachusetts and helped spin off its semiconductor group, creating what is now known as Allegro Microsystems and later helped LSI Logic acquire SEEQ Technology. Bob has been consulting with numerous start-ups until joining JVD in 2010. He is the author of several technical articles and white papers as well as numerous short and feature length screenplays. Bob is also a member of the Engineering Advisory Board of the College of Science and Engineering, San Francisco State University.