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ASIC Verification

July 30, 2015, anysilicon

In order to ensure how an ASIC will actually perform as a manufactured device, ASIC verification and simulations need to take place for the sustainability of functions in the device. ASIC verification can take on many different forms and depending on the type of designer, EDA tools or technology type; ASIC verification can be straight forward or much more complex. One or many forms of verification is essentially used to measure, test and validate design functionally and robustness.

 

Functional verification is one of the more popular methods for ASIC verification: functional verification essentially answers the question of does a proposed ASIC design actually do what it is supposed to? This means that the company has to first develop part of the ASIC or a number of different blocks within the ASIC and then run functional verification to which is verify proper functionality of the ASIC. Usually this requires a simulation environment with input vectors as well as outputs to measure for anomalies. Simulators and drivers will play certain stresses on the ASIC functions and the monitors will record metrics based on the performance of the device.

 

Even with all of these other forms of verification ASIC engineers often have to submit formal verification especially if a device will be entering mass production. In this form of verification engineers will have to prove or disprove the correctness through mathematical algorithms. This verifies the design of the chip in a formal proof. This ensures that the ASIC device functions both theoretically and physically.

See here a list of ASIC verification companies.