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Latch-Up

February 09, 2015, anysilicon

Latch-Up is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.

 

Latch-Up refers to the chain reaction that is initiated in a CMOS device due to a transient noise at the output which results in an incessant current flow through the CMOS device. In the event of a noise, a low impedance path is created which forms two parasitic Bipolar Junction Transistors (BJTs) within the CMOS device. Latch-Up wears out the device in a very short span of time and special care must therefore be taken to prevent. Using p+ guardband rings around the nMOS transistors and n+ guardbard rings around the pMOS transistors help in mitigating the impact of Latch-Up.