May 24, 2015, anysilicon
The time taken by a standard cell to process an input signal and produce a corresponding output signal is referred to as the propagation delay. Propagation delay is often measures from the time when the input signal has reached 50% of its maximum value (which typically is the VDD), till the time the output signal reaches the 50% of its maximum value.
Propagation delay decreases with scaling of the technology node and it directly affects the maximum clock frequency of the system. Higher clock frequencies are desirable to have higher throughput and to achieve maximum performance.