Static Timing Analysis

May 24, 2015, anysilicon

Static Timing Analysis (STA) refers to analyzing the design thoroughly to make sure that it operates at the specified frequency. It may involve developing timing constraints (like clock definitions, false paths, multi-cycle paths etc) to translate the design intent into a definition that is understood by the physical implementations tools for synthesis, placement, clock tree synthesis and routing. STA also monitors various parameters like the clock skew, signal slew and output load in order to meet the recommendations set by the foundries for any particular process.