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Timing Arc

May 24, 2015, anysilicon

Timing arc is an abstract notion of a timing dependence between the signals at any two related pins of a standard cell. Timing arcs are usually present in the timing libraries (liberty files), which are then used by the tool to perform static timing analysis and gate level synthesis of the design.

 

Timing arcs are of primarily three types- delay arcs which model the delay that the signal takes to propagate from one pin to another for a given input slew and output load; slew arc which models the transition time at the output pin of a cell for a given input transition and output load; and setup and hold arcs which model the constraints on the arrival time of a signal at the input of a flip-flop with respect to the clock.