Since its foundation, Barco Silex has been involved in hundreds of FPGA, ASIC and SoC designs, building up a well recognized expertise in the development of fully integrated SoC products. Relying on our design experience with ARM architectures, a large range of AMBA/AXI based IPs, together with a strong relationship with Faraday, we can deliver competitive SoC solutions.
Security and especially data encryption inquiries, thanks to our long term relationship with major players of the electronic payment market, have brought us advanced competences in this area. Barco Silex provides a comprehensive range of solutions and highly flexible cryptographic cores for standard algorithms like AES and various Public Key systems.
Image processing in general and video in particular is another key competence of the Barco Silex design team. As a logical outcome of many projects performed in the Barco group, and within several R&D projects, our engineers are experts at implementing real time, high performance image processing algorithms onto dedicated hardware. This is particularly true for image and video compression, where we also offer the best in class JPEG2000 IP cores.
Barco Silex provides crypto IP cores, making embedded security implementations easier and more flexible. The ASIC, SoC, FPGA Crypto IP cores are designed for optimized performance and minimal silicon cost. Encryption and embedded security expertise is build up through the realization of several projects for market leaders.
We have developed unique crypto engines, which provide both unrivalled performance and scalable reconfiguration capabilities optimized to your application, requirements, and technology constraints.
These innovative and break-through architectures are the result of strong foundations.
Barco Silex offers a comprehensive range of high quality solutions for JPEG 2000 applications. Our J2K IP cores can encode or decode JPEG 2000 images and video with unrivalled quality, high-speed and compact footprint. Our JPEG 2000 portfolio covers Intellectual Property (IP cores), reference designs and acceleration boards.
Barco Silex portfolio includes these fast JPEG IP cores. The optimized logic supports fast encoding or decoding of JPEG and M-JPEG streams. All the features of this family have been optimized to easily support motion JPEG implementation in hardware-based products.
Barco Silex’ JPEG IP cores are suitable for application that involve baseline-DCT JPEG compression. These flexible M-JPEG IP support monochrome, color or multi-scan formats. Our JPEG IPs fit all applications requiring high pixel throughput. These include printers, scanners, digital cameras, medical imaging, archiving…
Based on the experience in SoC design and IP development and in combination with our robust verification methodology, Barco Silex offers efficient and comprehensive solutions for widely used controllers such as DDR, DDR2, DDR3, NAND Flash, SRAM or DMA.
The many generic optional features available in our IP cores allow the customer to get the best possible trade-off between performance and area and to meet each and every customer’s application requirements.
Barco Silex offers a comprehensive range of high quality solutions for MPEG-2 applications. Our MPEG2 IP delivers unrivalled image quality.
Our MPEG-2 solutions meet the requirements of applications such as broadcast, production, digital cinema, video conferencing…
The VC-2 LD (Low Delay) codec is a lightweight video compression IP core with ultra-low latency
The VC-2 LD (Low Delay) Codec is ideally suited for ultra-low latency video transmission. The low complexity of the algorithm allows cost-effective compression of the video stream. A typical use case of the VC-2 LD codec is the reduction of the bandwidth required to transport HD, 4K and high frame rate video signals. The VC-2 Low Delay compression algorithm is a simple wavelet-based intra-frame codec. The algorithm is described in the SMPTE 2042 standard, “VC-2 Video Compression”.
The PCI Express (PCIe) Endpoint DMA is a highly configurable solution for any FPGA design requiring PCIe interfacing. It supports PCIe Gen 1, Gen 2 and Gen 3 interfaces, with up to 8 lanes. The DMA makes it easy to quickly transfer massive data between CPU and FPGA. The flexibility of the IP core enables many different use cases. The configuration of the Endpoint DMA can easily be adapted to the requirements of each project. The PCIe Endpoint DMA is already used in many applications such as Ethernet cards, high resolution image processing and others.