BaySand

USA

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BaySand is the leader in application configurable ASICs targeting short time-to-market and cost-effective ASIC solutions that include Standard Cell ASICs from 110nm to 16nm and with its unique and patented Metal Configurable Standard Cell (MCSC) technology, configurable DSP architecture (fcDSP), Arm processor experience, and expert design services.
BaySand provides all ASIC needs with world-class solutions. We offer a full spectrum of SoC Services and can offer any range of the IC design process from Front End design through to implementation, packaging and test.  Our Fabless manufacturing capabilities enjoy the benefits of our unique configurable IPs and our close relationships with leading semiconductor foundries such as Mie Fujitsu, TSMC, GF, and SMIC.

 

BaySand is a privately held fabless company, based in the Silicon Valley, San Jose CA.

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Services

ASIC Design Services & Implementation

BaySand experienced team provides full spectrum of SoC Services and can offer any range of the IC design process from Front End design through to implementation, packaging and test.  Our Fabless manufacturing capabilities enjoy the benefits of our unique configurable IPs and our close relationships with leading semiconductor foundries such as Mie Fujitsu, TSMC, GF, and SMIC.

ASIC turnkey Operation

BaySand offers professional services from Architecture and IP selection or generation to ASIC production and Supply Chain Management.

Crypto Coin & Block Chain ASIC

BaySand has created and is working on leading edge mining chips and system. We offer improved architecture to offer better mining.

Supply Chain Management

Full management of Operations and Manufacturing:

  • Package selection and design
  • Manufacturing
  • Test
  • Shipping
  • Characterization

RF & Mixed Signal

Expert design capabilities for RF and Mixed Signal.

IP Design and Licensing

BaySand offers expert IP design services.

Additionally, we offer our existing IPs for sale, or at a considerable discount if used in our ASICs.

IP Cores

1.6GHz Phase-Locked-Loop (PLL)

BaySand’s wide bandwidth PLL provides a solution for low jitter, low power, multi-phase clock synthesis, allowing maximum timing flexibility on complex System-on-Chip designs.

 

Highlights

● Designed on GlobalFoundries 40nm LP process

● Input reference frequency: 5 – 800MHz

● Output frequency range: Up to 1.6GHz

● Support programmable bandwidth

● Spread-spectrum reference tracking

● Support internal feedback (internal compensation) and external feedback (external compensation).

● Programmable reference clock divider, feedback clock divider, output clock divider (up to 512 division).

● Output counters: 9

– Support output counter cascading.

– Support programmable duty cycle output counter.

– Support 1/8 VCO clock period phase shift.

– Support output inversion

– All counters are synchronized on startup

● Support PLL cascading

● Support fractional division and SSC generation (digital logic is implemented outside the macro, in PLL wrapper RTL)

● ESD protection – HBM 2kV, CDM 500V

6.5Gbps Multiprotocol SERDES PHY (GF 65nm)

BaySand’s Multiprotocol SERDES PHY is designed to support a wide variety of serial protocols while providing competitive area, power, and performance.

The PHY supports data rates from 0.6Gbps to 6.5Gbps across copper and backplane channels.

Signal level optimization is available via linear equalization on the receive (RX) end, and transmit (TX) equalization on the transmit side.

The SERDES PHY can also be customized per application customization for various permutations of lane and common bundling. Moreover, the PHY supports various features like squelch with OOB support for SAS/SATA, TX idle for PCI Express 1/2 standards, and calibrated on-chip termination. In terms of testability, built in BIST, IEEE 1149.1/1149.6 (DC/AC) JTAG, and ATPG scan are all supported.

 

Highlights

● Designed on GlobalFoundries 65nm LPE process

● Full-duplex transceivers at serial data rete between 0.6Gbps to 6.5Gbps

● Requires supply voltage level of 1.2V, and 2.5V on second PMA voltage supply

● Calibrated on-chip termination

● TX equalizer (de-emphasis) up to -12dB

● Receive equalization up to 16dB

● Squelch circuit with programmable threshold for support of OOB in SAS and SATA and TX idle for PCIe1/2

● IEEE 1149.1(DC) and 1149.6 (AC) JTAG boundary scan support

● ESD coverage up to HBM 2kV and CDM 500V

12.5Gbps Multiprotocol SERDES PHY (GF 40nm)

BaySand’s Multiprotocol SERDES PHY is designed to support the most stringent signaling environments across a variety of serial protocols. The PHYs support data rates from 0.6Gbps to 12.5Gbps across copper and backplane channels, allowing for signal level optimization via adaptive equalization and support for decision feedback equalization (DFE) on the receive end, and TX equalization on the transmit side.

 

The SERDES PHY can also be customized per application customization for various permutations of lane and common bundling. Moreover, the PHY supports various features like spread spectrum clocking generation, squelch with OOB support for SAS/SATA, TX idle for PCI Express 1/2/3 standards, and calibrated on-chip termination. In terms of testability, built in BIST, IEEE 1149.1/1149.6 (DC/AC) JTAG, and ATPG scan are all supported.

 

Highlights

● Designed on GlobalFoundries 40nm LP process

● Full-duplex transceivers at serial data rete between 0.6Gbps to 12.5Gbps

● Requires supply voltage level of 1.1V, and 1.8V or 2.5V on second PMA voltage supply

● Supports spread spectrum clocking (SSC) for EMI reduction

● Calibrated on-chip termination

● Three-tap TX equalizer (de-emphasis)

● Adaptive continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)

● Squelch circuit with programmable threshold for support of OOB in SAS and SATA and TX idle for PCIe1/2/3

● IEEE 1149.1(DC) and 1149.6 (AC) JTAG boundary scan support

● ESD coverage up to HBM 2kV and CDM 500V

1.6GHz Phase-Locked-Loop (PLL) (GF 65nm)

BaySand’s Phase Locked Loop (PLL) is designed to meet the requirements of clock synthesis with best-in-class specification while keeping maximum flexibility in mind. It serves as an ideal clocking solution where best power, jitter performance, and area are required. The PLL has 6 output counters and supports up to 512 division of clock per counter – this provides an option for multi-phase, multi-ratio clock generation from each output – which can be extremely useful in special clocking scenarios. The PLL also supports wide bandwidth via dynamic bandwidth  programmability. Both external and internal reference feedback options are available. Spreadspectrum reference clock tracking is supported by default as well. Additionally, the counters support programmable inversion. Multiple PLLs can also be cascaded.

 

Highlights

● Designed on GlobalFoundries 65nm LPE process

● Input reference frequency: 20 – 800MHz

● Output frequency range: Up to 1.6GHz

● Support programmable bandwidth

● Support spread-spectrum reference clock tracking

● Support internal feedback (internal compensation) and external feedback (external compensation).

● Programmable reference clock divider, feedback clock divider, output clock divider (up to 512 division).

● Output counters: 6

– Support output counter cascading.

– Support 1/4 VCO clock period phase shift.

– Support output inversion

– All output counters are synchronized on startup

● Support PLL cascading

● ESD built in to support HBM 2kV, CDM 500V

Multi-Protocol Physical Coding Sublayer (PCS)

The PCS supports protocols using 8b/10b, 64b/66b, 128b/130b transmission code which data rates up

to 12.5Gbps*. 64b/66b code is used for IEEE 802.3 ethernet, and 128b/130b code is used for PCI

Express 3.0.

* The actual maximum data rate depends on PMA.

 

Supported Protocol Standards

  • PCI Express Gen1, Gen2, Gen 3
  • PHY Interface for the PCI Express (PIPE) 2.0
  • 1G Ethernet (GIGE)
  • 10G Ethernet (XAUI)
  • SATA 3.0 with OOB (Tx and Rx)
  • SAS 4 with OOB (Tx and Rx)
  • CPRI/JESD204B
  • 10G Base-R

Features

  • PCI Express 3.0 features.

○ Up to 8GT/s traffic.

○ 32 bits PMA parallel data width.

○ Up to 32 bits PIPE data width.

○ 8b/10b transmission code for Gen 1 and Gen 2 speed. 128b/130b transmission code for

Gen 3 speed.

○ Clock tolerance compensation.

○ Link data rate negotiation.

○ Beacon transmission and reception

○ Transmitter margining ( TxMargin )

○ Selectable de-emphasis ( TxDeemp )

○ Selectable signal swing values ( TxSwing )

○ Power management

○ Receiver detection

○ Loopback (Rx to Tx)

○ Symbol and Block lock synchronization.

  • 1G BASE-X

○ Line rate at 1.25 Gbps

○ Clock difference of 200PPM

○ Transmit State Machine (SM)

○ Receive SM

○ Synchronization SM

○ Auto-Negotiation

  • 10G BASE-X

○ Line rate per channel at 3.125 Gbps

○ Clock difference of 200PPM

○ 4 channels bonding

○ Transmit SM

○ Receive SM

○ Synchronization SM

○ Deskew SM

  • SATA Rev 3.0

○ PIPE 3.0

○ OOB signaling for both Tx and Rx

  • SAS 4

○ OOB signaling for both Tx and Rx

○ 40 bits PMA parallel data width.

  • 10G BASE-R

○ 64b/66b line coding

○ Scrambler, Descrambler

○ Gearbox

○ Block Synchronization

○ BER monitor

○ Elastic buffer (200 PPM)