eSilicon

USA

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eSilicon, a leading independent semiconductor design and manufacturing solutions provider, guides customers through a fast, accurate, transparent, low-risk ASIC journey, from concept to volume production. Explore your options online with eSilicon STAR tools, engage with eSilicon experts, and take advantage of eSilicon semiconductor design, custom IP and IC manufacturing solutions through a flexible engagement model. eSilicon serves a wide variety of markets including the communications, computer, consumer, industrial products and medical segments. Get the data, decision-making power and technology you need for first-time-right results.

Services

Taming the Complexity of ASIC Design

ASIC design involves the complex interaction of foundry process technology, IP design and integration, EDA tools and design methodologies, physical design, design for test, package design and product engineering. We focus on optimizing for the combination of power, performance, and area (PPA) appropriate for your device’s specific targets.

 

  • We have access to the leading foundry process technologies to 14/16nm through our partnerships with the world’s leading-edge foundries.
  • In addition to our vast third-party IP portfolio, we provide custom logic, memory, analog and I/O solutions to meet your specific needs, be they targeted for high performance or low power.
  • Our unique PPA-optimized design methodology is targeted to provide the best power, performance and area for your ASIC.

 

Concurrent Design for First-Time-Right ASICs

 

Close collaboration between our design, test, package, and process engineering teams results in a smooth transition of our designs to manufacture so that your design is testable and manufacturable with high yield. Our extensive experience with this holistic approach to ASIC design has yielded a proven track record of first-time-right designs and provides you with a quality ASIC solution and low total cost of ownership.

Sophisticated Packaging Expertise

Packaging expertise at eSilicon covers many disciplines, from the traditional to 2.5D and 3D. We take a holistic approach to package selection, identifying the solutions best suited for a given application. The considerations made at the very beginning of a project include the following:

 

  • Signal count/type
  • Signal integrity
  • Power delivery
  • Isolation/crosstalk
  • Signal transition
  • Electromagnetic interface (EMI)
  • PCB routing options
  • Space requirements
  • Cost considerations
  • Thermal considerations
  • Volume vs. assembly source
  • Reliability considerations

 

Signal Integrity Team

 

Our signal integrity team is not as an afterthought of the design process. Instead, signal integrity at the die, package and system levels is considered up front. Our team is a scalable extension of your own and we can either complement your own capabilities or add capabilities in complex electrical performance modeling. Rules of thumb may be a good starting point, but we do not rely on these to determine the outcome. Before a part is ever constructed, we can work with you to determine what services make the most sense for a given application and what needs to be done to overcome any performance concerns you may have.

Custom Memory IP and I/Os

eSilicon’s IP solutions include foundation and custom memories that are different from standard off-the-shelf solutions. We tailor our solutions to fit seamlessly into your design and test flow with custom features. Our memories are optimized across the spectrum of performance, power, area, and yield to address your specific market requirements. eSilicon offers one of the broadest ranges of expertise in embedded memory IP among semiconductor IP providers, and we have been a provider of customer-specific memory IP to leading integrated device manufacturers (IDMs), fabless semiconductor companies (FSCs) and OEMS for over a decade.

 

In addition to memory IP, we offer process development services to IDMs and foundries during early-stage process bring-up:

  • SRAM bit-cell development
  • Test-chip design for process development and yield enhancement
  • CAST™ device characterization tool and services: Component Auto-generation System for Test-chip creation

 

eSilicon STAR Navigator: Search, Select and Try IP Online

 

Now you can get immediate answers to your power, performance or area (PPA) questions with pre-loaded data for eSilicon® memory compilers and I/Os using eSilicon STAR Navigator.

The Right Partner for the Right Chip

eSilicon partners with key suppliers in the areas of semiconductor intellectual property (IP) and manufacturing, including foundries, packaging and test houses. These partnerships enable a seamless flow from concept to production.

 

We evaluate suppliers based on their technology, considering the performance of each element in the supply chain for performance and reliability for each customer’s design.

 

Close, long-term relationships with our suppliers mean we can act quickly and effectively against adverse industry conditions, such as the 2010 materials shortage and the 2011 catastrophe in Japan.

 

As an independent semiconductor design and manufacturing solutions (SDMS) provider, we are free to work with any foundry or IP supplier. We explore tradeoffs in all dimensions to implement the right solution for each design:

 

  • Process/foundry
  • NRE/ASP
  • Die/package
  • Standard IP/custom IP

Test Engineering

Test engineering is one of the final critical steps before your device is ramped into production. eSilicon’s test engineering services move your product from design to production efficiently via our in-house engineering team. Our team will manage your device through the final stage before volume production using a broad range of expertise in all facets of ASIC device testing. Using our proven flow, our goal is to get your product ramping to production as quickly as possible using our advanced methodologies, processes, and years of experience to choose the right path for your ASIC design.

 

In-House ASIC Production Test Engineering Expertise

We have in-house expertise in:

  • Test plan development
  • Design-for-test (DFT) methodologies
  • Test pattern conversion
  • Test hardware development
  • Test program development for digital, high-speed interfaces and mixed-signal devices
  • A broad range of tester platforms

Production Device Tests

Our engineers are experienced in the full range of device tests, including:

  • Scan testing using the following fault models:
    • Stuck-at scan
    • Transition scan
    • Path-delay scan
  • Memory built-in self test (MBIST), including:
    • At-speed testing and repair
  • High-speed interfaces, including:
    • DDR1 through DDR4
    • Ethernet
    • LVDS
    • MIPI
    • SerDes (PCIe and XAUI)
    • USB 3.0
  • Phase-locked loops (PLLs) and delay-locked loops (DLLs)
  • USB 1.0 and 2.0
  • Digital-to-analog converters (DAC)
  • Analog-to-digital converters (ADC)

 

Optimize Yield, Product Cost and Performance Metrics

Foundry Engineering

 

Foundry engineering support provides safeguards for the high non-recurring engineering (NRE) cost of implementing new products. eSilicon provides the fab device and integration experience for first-time tapeout success. Tapeout support includes LVS (layout vs. schematic), DRC (design rule check), MEBES (manufacturing electronic beam exposure system) review and support, resulting in successful tapeouts.

 

Product Engineering

 

Product engineering support safeguards product costs through effective yield management.

 

An experienced engineering team establishes baselines and maintains yield and performance targets. The baseline is established with product characterization which reduces production ramp risks. This baseline allows the team to efficiently root cause and troubleshoot deviations in production.

 

Investment in tools integrates data from all suppliers. These tools, such as the Genesis yield analysis tool, allow efficient, complete data analysis of complex tasks when combined with our own eSilicon® STAR Tracker production management tool.

 

Yield Management Program Overview

 

The yield targets are maintained through periodic reviews. We statistically review process WAT (wafer acceptance test), sort yield and final test yield data trends to continually optimize yield using a fully integrated yield management system. We also establish wafer yield rejection criteria with the fab early in the process to control both cost and quality.

 

We perform a variety of analyses to reduce the occurrence of random low-yield lots. Analysis may include:

 

  • Review of yield correlation to WAT data
  • Review composite yield information (stack maps)

 

IP Cores

Custom Memory IP and I/Os

eSilicon’s IP solutions include foundation and custom memories that are different from standard off-the-shelf solutions. We tailor our solutions to fit seamlessly into your design and test flow with custom features. Our memories are optimized across the spectrum of performance, power, area, and yield to address your specific market requirements. eSilicon offers one of the broadest ranges of expertise in embedded memory IP among semiconductor IP providers, and we have been a provider of customer-specific memory IP to leading integrated device manufacturers (IDMs), fabless semiconductor companies (FSCs) and OEMS for over a decade.

 

In addition to memory IP, we offer process development services to IDMs and foundries during early-stage process bring-up:

  • SRAM bit-cell development
  • Test-chip design for process development and yield enhancement
  • CAST™ device characterization tool and services: Component Auto-generation System for Test-chip creation

eSilicon STAR Navigator: Search, Select and Try IP Online

 

Now you can get immediate answers to your power, performance or area (PPA) questions with pre-loaded data for eSilicon® memory compilers and I/Os using eSilicon STAR Navigator.

High-Bandwidth Memory (HBM) Solutions

eSilicon HBM1 and HBM2 PHY, DLL and I/O Libraries

eSilicon also develops HBM Gen1 and HBM Gen2 PHY, DLL and I/O libraries, catering to a wide variety of customers and market segments from 28nm to 14nm/16nm. Our HBM Gen2 I/O library includes support for programmable driver strengths, embedded ESD/Decaps, internal programmable VREF generators, receiver power-down modes and can support up to 2Gb/s data rate with clock speeds of up to 1GHz.

 

Key features of eSilicon’s HBM Gen 2 PHY IP:

  • 1GHz operation with data rates of up to 2Gbps/pin
  • Support both 1:2 and 1:4 serialization/deserialization modes
  • Eight channels with 1024 DQs per HBM Gen 2 stack
  • Lower power I/O interface with unterminated DATA/ADDRESS/CMD/CLK interfaces
  • Pseudo-differential receiver with internal programmable VREF
  • One Read Strobe and one Write Strobe (RDQS/WDQS) for every 32 DQs (DWORD), one DBI/DM for every eight DQs, one parity bit for every DWORD
  • Write eye/Read eye training support
  • Built-in FSM for interface training
  • Programmable internal VREF generator support for fine tuning
  • Built-in status and control of configuration registers
  • Pseudo channel mode support

 

eSilicon 2.5D Concept

 

eSilicon is connected to all levels of the semiconductor manufacturing supply chain: fabs, test and assembly companies, EDA companies and design houses. If you are interested in doing your first 2.5D or 3D project, we can help you make the right decisions. eSilicon will manage the entire supply chain using the fabs and assembly and test houses that are ready for 2.5D and 3D-ICs. eSilicon is already active in 2.5D and expects to be an early adopter of production-ready 3D technology

TCAMs and BCAMs: Ternary and Binary Content-Addressable Memory Compilers

eSilicon embedded binary and ternary content addressable memories (BCAMs and TCAMs) have been provided to networking customers for over 10 years, helping these customers meet the demand for wire-speed packet processing, access control lists and other requirements of high-bandwidth delivery. eSilicon binary and ternary CAMs are available in geometries from 14nm/16nm to 180nm.

 

They are available now through eSilicon. eSilicon is participating in TSMC’s Open Innovation Platform™ IP Alliance Program, which includes quality assessment of this eSilicon IP through the TSMC9000™ Program. All 28nm memory compilers are silicon-proven and available through this program.

 

Please contact us at ipbu@esilicon.com for our TCAM white paper, High-Performance Classification Using Embedded Ternary Content Addressable Memory. You can also register on our website then download the TCAM white paper.

 

Features

 

  • 14nm/16nm TCAM
  • > 1GHz operation
  • Up to 1.25 BSPS under worst-case operating conditions, 14nm/16nm
  • Up to 2.5 BSPS under typical operating conditions, 14nm/16nm
  • Up to 160Kb compiler, 40Mb cascading table size
  • Up to 160 bits per word
  • Single-cycle compare operation
  • Partial pipelined search and smart power management
  • Hardened priority encoders
  • Column redundancy for higher yield
  • Multi-width search mode to switch dynamically between IPv4 and IPv6 searches
  • Built-in self-test (BIST) and built-in self-repair (BISR) for higher test coverage during wafer sort and production

 

Availability

 

eSilicon TCAMs are available now. Silicon results and data sheets are available from ipbu@esilicon.com, or visit the eSilicon® STAR Navigator IP exploration environment.

Register-File Memory Compilers

eSilicon has designed single-port and two-port register-file memory compilers catering to wide variety of market segments.

 

Ultra-Low-Voltage and Ultra-Low-Power Register Files for the IoT Spectrum

 

We are gradually being surrounded by a network of physical objects or “things” embedded with electronics to make them “smart.” These devices are mostly on and listening to incoming data. Therefore, optimizing for very low voltage and power is critical for maintaining long battery life. Internet of Things (IoT) medical and wearables customers benefit from eSilicon’s ultra-low-power and ultra-low-voltage register files for these extreme requirements.

 

High-Speed Register Files for Networking and Big Data Analytics

 

IoT is expected to generate large amounts of data from the plethora of “things” from diverse industries and locations, thereby increasing the need for improved performance and bandwidth in networking and communications. Networking and communications customers rely on the performance of eSilicon’s high-speed register files at 40nm, 28nm, 16nm and 14nm to meet the demanding wireline speed requirements of networking applications and the sophisticated cloud-based processing of Big Data.

 

Find out more about eSilicon STAR Navigator: Search, select and try eSilicon IP online at no cost or obligation.

 

Please contact us at ipbu@esilicon.com  for technical documentation or if you would like to learn more about our custom memory IP and I/O offering.

High-Speed Single-Port Cache Memories

Silicon has designed custom high-speed single-port cache memories that are optimized to meet the high-performance requirements of industry-standard processor cores.

 

High Performance for the Low-Power Market

 

The performance of smart phones, handheld devices, digital TVs and other power-sensitive devices is often limited by the performance at which the processor cores can run. At the same time, the performance of processor cores is often limited by the performance of memory instances used in the L1 cache of the processor core. eSilicon has delivered fast-cache memories to customers in the low-power process segment at advanced nodes down to 28nm. These cache memories deliver one of the highest levels of performance in the low-power market segment.

eSilicon’s philosophy for developing cache memories is to first meet the end customer’s performance requirements. Then we map the circuitry to the customer’s other key metrics, such as low leakage or small area. This philosophy has helped us consistently deliver fast-cache memories that meet customer requirements.

 

Please contact us at ipbu@esilicon.com if you would like to learn more about our custom IP offering.

 

Search, select and try eSilicon® IP online at no cost or obligation. Find out more about eSilicon STAR Navigator (formerly IP MarketPlace).

Interface IP

General-Purpose and Specialty I/O Libraries

 

eSilicon offers a broad range of 14nm-180nm general-purpose I/O and specialty I/O libraries optimized for various process technologies and applications. All interface IPs are optimized for the best performance and designed to meet full ESD and latch-up tolerance requirements.

 

 

Please contact us at ipbu@esilicon.com for technical documentation or if you would like to learn more about our custom memory and I/O offering.

 

eSilicon Interface IP Offering

 

Process   Foundry I/O Libraries
180nm G IDM LVCMOS
130nm G TSMC DDR, LVCMOS, Thermal diode
130nm SLP Tower 1.2V GPIO, LVCMOS
90nm G TSMC DDR, Thermal diode
65nm LP UMC multi-DDR(2/3/3L/LP2/LP3), SDIO, eMMC
65nm LP TSMC DDR, LVCMOS, Universal PHY (DDR/RLDRAM/SPI/Hypertransport)
65nm LPE GlobalFoundies LVCMOS
40nm G TSMC LVCMOS, I2C, LVDS, SLVDS
multi-DDR(2/3/3L,LPDDR2)
40nm LP TSMC LVDS, SLVDS, I2C, 1.8V/3.3V eMMC5.0
28nm HPM TSMC LVCMOS, I2C, LVDS, multi-DDR(3/3L/4)
1.8V/2.5V/3.3V GPIO
28nm HPC TSMC 1.8V/2.5V/3.3V GPIO, LVDS, 1.8V ONFI3.0
HBM2 IO (In development)
28nm HPP  GLOBALFOUNDRIES HBM IO
28nm HLP/HPM UMC 1.8V GPIO, 1.8V/3.3V GPIO
28nm HPC UMC 1.8V GPIO (In development)
1.8V/3.3V GPIO (In development)
14nm LPP Samsung 1.8V/2.5V/3.3V GPIO (In development)

 

Search, select and try eSilicon® IP online at no cost or obligation. Find out more about eSilicon STAR Navigator (formerly IP MarketPlace).