HDL Design House delivers leading-edge digital, analog, and back-end design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores, developed and verified using Cadence tools and flow, and component (VITAL) models for major SoC product developers. Founded in 2001 and currently employing 120 engineers working in three design centers in Serbia and Greece, HDL Design House’s mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2013 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS).
IP & SoC/System verification:
System and SoC architecture:
SoC top level integration and verification:
Runs at speeds of up to 4 Gbps per lane Supports between 1 – 32 lanes Uses data scrambling to reduce EMI signature Targeted for low-power, high-speed digital video data trans- mission Performs data alignment and synchronization Includes link monitoring functions Supports a variety of video resolutions (HD, Full HD, Cinema Full HD, 4K x 2K) Allows for the transmission of 3D video Features color depths of 18,24, 30, & 36 bits per pixel Supports video refresh rates of 60, 120, 240 & 480 Hz.
The JESD204B RX Physical Coding Sublayer IP Core (HIP610) enables the reception of data via a configurable number of lanes from a Deserializer interface, while guaranteeing data alignment and frame synchronization. The HIP610 IP Core performs 8b/10b decoding, frame recovery, lane alignment, descrambling, and data demapping functions. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP610 IP Core supports configurable number of DAC ports, each one having a width of up to 32 bits. The HIP610 IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers.
The JESD204B TX Physical Coding Sublayer IP Core (HIP600) enables the transmission of data via a configurable number of lanes from a Serializer interface. The HIP600 IP Core performs data mapping, scrambling, alignment character insertion and 8B/10B encoding functions. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface. The HIP600 IP Core offers the possibility to modify the behavior of the design based on the application requirements. This is done through the use of the design parameters, as well as via the Configuration Interface by programming the configuration registers.
The Physical Coding Sublayer (PCS) IP Core enables transmission and reception of data via 8-Lanes SerDes interface. It is able to multiplex a synchronous digital stream of data over 8 Lanes, while guaranteeing data alignment and super-frame synchronization. The PCS is responsible for idle sequence generator, lane striping and encoding for transmission and decoding, lane aligment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link.
CSI-2 (Camera Serial Interface) Transmitter IP core is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs packing in form of long packets, and Short packets, and sends them via PPI interface to the Host processor. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, the CSI-2 Transmitter IP core is fully compliant to MIPI Alliance’s CSI standard, as well as to AMBA’s AHB specification.
Transmitter is to implement the HDMI formatting of the input video and audio data, and interface to a serializer for direct transmission onto the HDMI cable. This IP core supports HDCP authentication and synchronization, identification of the RX capabilities via E-EDID on the DDC, hot plug detection, and a simplified implementation of the CEC protocol. The IP is composed of an HDMI 1.4 core and its physical Layer devices (PHY) in 65nm, 40nmLP, and 28nmLP technologies.