Rivlan has focused on high-performance IC design for analog, RF and mixed-mode applications.  It brings to customers more value by offering system expertise in defining a product and solving all related system issues, before selecting an appropriate technology and proceeding to the IC implementation.  Apart from our traditional expertise in wireless, GPS and video products our strength extends to industrial, instrumentation, medical, sensor and RFID applications.  Rivlan possesses extensive hands-on expertise in the entire ASIC development cycle – from product definition through transfer to production.  Our services include the entire design flow starting from system specification, through block level design down to transistor level implementation, physical design and prototype measurements. Depending upon the scope of your needs, Rivlan offers both short-term and/or long-term support.  By integrating innovative IC design solutions with proven methodologies and the most advanced fabrication processes available, we will enable you to maximize your project investment.


Chip System specifications

  • Reviewing or designing the ASIC system specification for its monolithic realization.
  • Selecting an appropriate system and circuit topology for the chip implementation.
  • Installing device models for the chosen technology on the circuit simulator tool.

Block level design

  • Designing the ASIC block specifications.
  • Performing feasibility study of the ASIC and its critical blocks.
  • Documenting the feasibility study.
  • Holding a design review on the feasibility study.

Chip design

  • Performing electrical assembly and simulations of the entire chip.
  • Extracting the ASIC netlist from layout, extracting the layout parasitics and performing simulations from the layout-extracted netlist.
  • Documenting the chip electrical design and its simulations.
  • Holding a design review for the ASIC electrical design.

Layout design

  • Assisting the Client with, or designing the chip layout.
  • Performing floorplan design.
  • Performing detailed block layout design.
  • Buses and supply lines design.
  • Top level layout design.
  • Holding a design review for the ASIC electrical and layout design.

Chip verification and tapeout

  • Performing layout verification, LVS and DRC.
  • Layout parasitic extraction and simulations.
  • Layout final corrections.
  • Preparation for tapeout.
  • Tapeout.

Chip measurements and characterization

  • Assisting the Client with, or performing the design of measurement setup.
  • Assisting the Client with, or performing the ASIC prototype measurements.
  • Discussing with the Client the final results of the ASIC prototype measurements.
  • Recommending the final ASIC implementation improvements.

IP Cores

RF blocks

2.4GHz LNA – NF = 0.8dB, IIP3 = -12dBm, S21 = 14dB in 0.18um TMSC process


5.2GHz Mixer – NF = 6.6dB, IIP3 = -3.9dBm, Conversion gain = 11dB in 0.18um TMSC process


6.6-8.0GHz VCO – PN = -153.0dBc/Hz@20MHz, PN = -117.5 dBc/Hz@0.4 MHz, in 65nm TMSC process


1.296GHz PLL – low spurs < -60dBc, 1V supply in 90nm UMC process


low jitter PLL – wide range of 135–945MHz in 90nm UMC process


ultra-wide range PLL – ultra-wide range of 100-3200MHz in 65nm UMC process


PSI2488-U9 GPON ONT SERDES – 1V and 1.2V supply in 90nm UMC process


USB 2.0 interface – in TSMC 0.18um and LSI 0.12um processes


DVB-H TV-tuner (radio portion) – in 0.13um TSMC process


GPS receiver (radio portion) – in 0.13um TSMC process