SigIntegrity Solutions

India

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SigIntegrity Solutions specializes in ASIC co-design, IC package design, Signal Integrity analysis & Electromagnetic modeling. We support IC package co-design SI/PI activity before & after silicon tape-out release. Pre-silicon tapeout co-design activity ensure optimized silicon in term of best performance, lowest cost & complexity at package & PCB level. We ensure optimum ASIC floor plan, bump-order, S:P:G ratio and all other silicon parameters through extensive SI/PI co-design simulations.

 

Post-silicon package design activity includes optimized package layout & design using minimum possible layer counts for lowest possible cost, BGA-pitch & BGA-ball planning to ensure minimum PCB routing complexity, SI/PI co-design analysis, output file generation for fabrication, co-ordination with substrate manufacturing house & assembly house.  We support flipchip & wirebond package designs using standard BT organic substrate, low-loss organic substrate & LTCC substrate for mmwave design.

 

We also provide system level (chip-package-PCB)  Signal integrity & power integrity analysis solutions, fullwave s-parameter extraction & electromagnetic modeling of the interconnects for all kinds of High speed interfaces and generate system design guidelines (DDR3, DDR4, multi-gigabit Serdes,  PCIe gen3 & gen4, XAUI, HDMI, SATA, USB, chip-to-chip IO, FPGA IO)