SigIntegrity Solutions

India

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SigIntegrity Solutions specializes in ASIC co-design, IC package design, Signal Integrity analysis & Electromagnetic modeling. We support IC package co-design SI/PI activity before & after silicon tape-out release. Pre-silicon tapeout co-design activity ensure optimized silicon in term of best performance, lowest cost & complexity at package & PCB level. We ensure optimum ASIC floor plan, bump-order, S:P:G ratio and all other silicon parameters through extensive SI/PI co-design simulations.

 

Post-silicon package design activity includes optimized package layout & design using minimum possible layer counts for lowest possible cost, BGA-pitch & BGA-ball planning to ensure minimum PCB routing complexity, SI/PI co-design analysis, output file generation for fabrication, co-ordination with substrate manufacturing house & assembly house.  We support flipchip & wirebond package designs using standard BT organic substrate, low-loss organic substrate & LTCC substrate for mmwave design.

 

We also provide system level (chip-package-PCB)  Signal integrity & power integrity analysis solutions, fullwave s-parameter extraction & electromagnetic modeling of the interconnects for all kinds of High speed interfaces and generate system design guidelines (DDR3, DDR4, multi-gigabit Serdes,  PCIe gen3 & gen4, XAUI, HDMI, SATA, USB, chip-to-chip IO, FPGA IO)

Services

IC Package design

Our package design service includes:

  • Wirebond
  • Flipchip
  • System-in-package
  • 3D packaging (coming soon)

 

Our package design flow ensures

  • BGA-pitch & BGA-ball planning to ensure minimum PCB routing complexity
  • Optimum package layout & design using minimum possible layer counts
  • Ensure design for minimum possible packaging cost.
  • SI/PI co-design SSN analysis
  • Extract package s-parameter models
  • Output file generation for fabrication
  • Coordinate with substrate vendor for design rules and substrate manufacturing
  • Support chip-package assembly vendors

 

We can support following substrate options for any packaging needs:

  • Standard organic package
  • Low-loss organic package for ultra-high speed design (> 28gbps)
  • low loss LTCC substrate based design for mmwave frequencies
  • Packaging of mmwave passive RF components using low-loss alumina substrate.

 

Low-volume packaging at low cost is always a challenge for any test-chip development. We can very well support low-volume requirement at relatively lower cost.

ASIC co-design

We ensure perfect ASIC-package-system co-design and account all system impact on silicon before its release. our ASIC co-design solution includes:

  • Support Package design activity for the identified package at ASIC architecture level.
  • Involve during finalization of ASIC floor planning and power planning for optimal performance at package and board level
  • Proper ASIC planning to ensure lowest cost & complexity at package & PCB level
  • Perform silicon-package feasibility analysis
  • IO ring generation recommendations with best pad-placement, pad-order & bump assignment (signal/ power/ ground) for best floorplan /package co-design prospective
  • Bump pitch & bump pattern planning
  • RDL routing recommendations for connecting bump to pad in SoC.
  • Signal, Power, ground bump assignment recommendations for best power delivery to SoC & meeting routing complexity/ design-rules of package
  • Core power implementation planning.
  • On-chip inductor electromagnetic modelling
  • Estimate package decoupling requirement and amount of on die decoupling capacitor to reduce SSN
  • Perform Signal integrity, power integrity analysis to ensure best signal quality and performance at system level.
  • Perform worst case timing analysis at system level and ensure good eye opening before silicon tape-out

 

Signal Integrity & Power Integrity

We have extensive expertise on system PCB level Signal integrity & power integrity analysis solutions as below:

  • High speed serial/parallel interface analysis and design guidelines (DDR3, DDR4, multi-gigabit Serdes,  PCIe gen3 & gen4, XAUI, HDMI, SATA, USB, chip-to-chip IO, FPGA IO)
  • Signal integrity & power integrity co-design SSO modeling
  • pre-layout & post-layout SI/PI analysis.
  • IBIS/IBIS-AMI based system level SI evaluation.
  • Routing studies, termination schemes, stackup design & analysis.
  • Trace & via design for controlled impedance using EM solver.
  • Full-wave EM modeling based s-parameter extraction

 

  • Analyze and verify power supply quality at chip, package & board level.
  • Power integrity AC & DC analysis
  • Target impedance estimation and optimization.
  • Decoupling cap estimation and optimization
  • Power-ground loop inductance & stackup optimization.
  • Time-domain power integrity noise estimation.

Electromagnetic modeling

We have extensive experience on 3D EM fullwave modeling. We can support all kind of High speed interconnects (post-layout PCB & package, connectors, traces geometry, via ) for s-parameter extraction modeling.

We also support EM modeling of passive RF components & their optimization for LTCC & Alumina substrate.