Silicon And Beyond

India

silicon-and-beyond-logo 180

Silicon And Beyond (Formerly known as SilabTech) – The High Speed SERDES IP Company, focus on very low power interconnect solutions for the most demanding applications. The company was founded in 2012 by a group of senior Analog designers who worked together at TI and since its inception had tape out many SERDES and other Analog IP Cores for world class customers.

 

The company qualifies its products on advance silicon processes 28 & 40nm and various foundries such as TSMC, GF & SMIC. Silicon And Beyond design process is leveraging on IPExcel Design Automation Tool that was developed to ensure standardize design process and documentation as well as optimize re-use of company IPs. Silicon And Beyond has a well-equipped lab that is capable of characterizing high speed SERDES IP and running complete compliance tests.

 

Main Applications: Consumers, Industrial, Telecom, RF and Servers. Silicon And Beyond has a unique Low Power ADC/DAC solution for RF and Industrial application which is also silicon proven.

IP Cores

1.25-12.5 Gbps Multi-Standard SERDES PHY

Silicon And Beyond’s Multi-standard programmable SERDES IP was designed and validated on various foundries and advance nodes 28 & 40nm.

The SERDES can be used as a Single or a Multi lane configuration- Reach the 100 Gb/Sec interconnect with our 8 Lanes design.

Support the following standards:
PCIe Gen 1-2-3
SATA Gen 1-2-3
USB SuperSpeed 3.0 & 3.1
10GBase-KX-4
10Base-KR (SR)
CEI-OIF 11SR
XAUI
SGMII
HSSTP (High Speed Serial Taping Port)- Debug Port
Video-By-One VbyOne
Display Port
HMC- Hybrid Memory Cube Interface
CPRI- Common Public Radio Interface
PON/GPON/EPON support via XFI

TSMC 28HPM – Silicon Proven
SMIC 40LL- Silicon Proven
GF 28SLP- In Design

GF 40LP 6.25Gbps- silicon proven

Silicon And Beyond support complete PHY Solution for JEDEC JESD204B (SERDES + Controller).

Data Rate programmable 1.25-12.5 Gbps

SERDES IP Core can be migrated to other Tech node; 65nm and up to 180nm for lower speeds- Contact us for more details.

Deliverables

  • Specification and integration document.
  • Physical models : LEF, GDSII
  • Spice models for LVS.
  • CLP models for low power aware designs.
  • Timing models (.libs)
  • Simulation models (behavioral and board simulation)
  • DFT models and test vectors
  • Reference Board with FPGA
  • Characterization and compliance reports.

 

Supported Foundries:

TSMC 28 HPC/HPM ; HPC+

GF 28SLP; 40LP

SMIC 40LL

 

Complaint Standards:

USB 3.0/3.1; PCIe 3; SATA 3; DisplayPort; XAUI; SGMII; CEI-11G; CEI-6G; 10G-BASE-KR; HMC; VbyOne; DisplayPort; CPRI

 

 

High Speed ADC/DAC 8bit/3.52Ghz GF 40LP

  • Analog to Digital Converter (ADC) design is based on interleaved SAR architecture, where each SAR ADC work on 440MHz and 8 ADC’s are interleaved to achieve 3.52GHz data/sampling rate.
  • The SAR is based on asynchronous clocking mechanism which helps in optimizing the settling and decision time in each individual ADC.
  • The differential design support the settling of common mode internally.
  • Input signal voltage – 500mVpp differential.
  • The ADC design internally terminates the ADC input with 100 ohms differential resistor with common mode of 900mV.
  • The data from ADC are available on each phase of 3.52GHz clock or can be provided in <63:0> format on 440MHz ADC clock.
  • DAC: 8-bit Differential Current Steering DAC is based on 1.1V supply.
  • DAC: The design supports 50 ohms Differential Termination with output voltage swing of 500mVpp differential. The output voltage swing is programmable from 400mVpp to 600mV differential.
  • The DAC supports common mode voltage programmability from 0.8V to 1.1V (supply).
  • This DAC can take input data at different input rates and re-align the data internally, like 64 bit data at 440MHz or 32 bit at 880MHz.

SB-JESD204B 12.5G SERDES

Silicon And Beyond JESD204B SERDES is running up to 12.5 Gbps in a single lane.

  • JESD204B SERDES PHY IP running up to 12.5 Gb/Sec in a single lane
  • The IP can be designed with Single/Multi lane configurations- Reach the 100Gb/Sec interconnect with our 8 Lanes design.
  • JESD204B Controller (PCS) is available either as bundle or as a Stand Alone.
  • Lowest Power and Area in the industry
  • Customization Services for specific applications, protocols and processes.
  • Transmit Driver with programmable output swing 100 mV 1200 mVp2p Pre/Post cursor Transmit equalization range 0 ¡V 12db with 20mV programmability step Adaptive Receiver equalization (CTLE + DFE) for channel with insertion loss up to 30db at 6GHz
  • Embedded low jitter phase-locked-loop (PLL) with 0.8ps rms RJ (filtered with single pole 4MHz HPF) Spread spectrum clock generation with up to 5000ppm down-spread
  • Beacon, Out-of-band (OOB) Signaling, Low-Frequency-Periodic-Signaling (LFPS), Auto-negotiation (AN) Signaling supported
  • Standard Interface with SOC- Standard specific PCS layer provided with the SERDES enables standard interface with the SOC
  • DFT & Test Rich in DFT features (AC-JTAG, Eye-scan, Loop-back, RX Sensitivity BIST, TX level BIST, PLL BIST) Stuck-at & TFT scan for digital Boundary scan (Extest) for integration with SOC scan compressor Tests can be done on low cost digital test

 

The IP can be designed with Single/Multi lane configurations- Reach the 100 Gbps interconnect with our 8 Lanes design.

APLL 0.1-6.25Ghz

Silicon And Beyond Ring Based Analog PLL is suitable for highly accurate clocking systems where designers do need to keep the PLL behavior flexible and therefore On-The-Fly setting is important.

  • Analog Phase Locked Loop (APLL) Output clock frequency range 0.1-6.5 GHz
  • Input clock frequency range 12-100MHz
  • Supports pre-division of input clock Integer and Fractional Multiplication supported Post-division of output clock supported
  • Allows band-width programmability
  • Supports power saving modes to selectively disable unused output clocks
  • Programmable Spread Spectrum Clock Generation (SSCG) supported
  • Allows in-band SSC propagation
  • 4 phases of output clock available
  • Support SERDES Standards such as: JESD204B, M-PHY, C-PHY, D-PHY, PCIe, SATA, USB3.0, 10GBase-KR/KX4, 1000BASE-KX, CEI-6G-SR

The PLL support wide range of outputs from 0.1Ghz and up to 6.5Ghz – programmable on the same PLL.

Meets low output clock jitter compatible to requirements of multiple high-speed SERDES standards :

  • PCI-Express I, II and III
  • Serial ATA I, II and III
  • USB3.0, USB3.1
  • HDMI
  • MIPI Gear 1, 2, 3 Series A/B
  • 10G-base-KR, 10G-base-KX4, 1000-base-KX
  • XAUI
  • JESD204B
  • OIF CEI-6G, CEI-11G

Additional Technologies: TSMC 28HPM; GF 28SLP; SMIC 40LL and can be migrated to any other process nodes upon demand.

JESD204B SERDES Controller

JESD204B SERDES Controller IP support independent Rx and Tx lanes.

Silicon And Beyond JESD204B controller can support Single/Multi lanes configurations- Reach the 100 Gbps interconnect with our 8 Lanes design.

SilabTech Controller is available either as bundle along our SERDES IP or as a Stand Alone IP (Soft Marco).
Data Rate programmable 0.3-12.5 Gbps and even higher speeds.

Supported features (Tx and Rx)
• JESD204b – subclass 0 and 1
• Programmable width stream interface (128b or 64b)
• HW configurable FIFO
• Configurable JESD modes
• L = 1,2,4,8
• N = 7 to 16
• N’ = 8,12,16
• CF = 0, 1
• CS = 0, 1, 2
• F = 1,2,4
• K = any even number > JESD standard limit
• HD = 0
• APB based programming interface with SOC

Controller customization can be discussed to enable specific application optimization.

USB 3.0 SERDES SMIC 40LL

  • USB 3.0 / 3.1 Support Standard Interface to SOC (PIPE3.0, APB, IEEE1500 8pin)
  • Wire-bond/flip-chip/Copper Pillar package supported
  • Support for full swing and low power swing transmitter operation.
  • Transmit equalization with nominal 3.5dB de-emphasis support
  • Receiver with adaptive Continuous Time Linear Equalization (CTLE)
  • Embedded Low Jitter PLL with 2.4ps rms RJ (filtered with USB3 mask)
  • PLL supports Spread Spectrum Clocking (SSC) generation with downspread of 5000ppm
  • Support for Low Frequency Periodic Signaling
  • Performance- Low active and stand-by power
  • All power-saving modes implemented for aggressive power saving.

Type Hard IP

Maturity Silicon proven

Market Category Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

Bus Interface PIPE, APB, P1500

USB3.0   USB3.1

Protocols40nm/SMIC/LL

MIPI C+D Combo PHY upto 2.5 Gbps TSMC 40 LP

  • Standard Interface with SOC – PPI compatible interface with higher protocol layer APB Interface for IP functional mode configuration IEEE1500 8pin interface for DFT configuration
  • HS & LP receivers & LP transmitter integrated Support extension to multiple lanes Embedded Low Jitter PLL
  • DFT & Test – Stuck-at & TFT scan for digital Boundary scan (Extest) for integration with SOC scan compressor Automated functional test – AC JTAG, Loop-back, RX sensitivity BIST, PLL BIST
  • Flexible number of Tx & Rx Lanes per your application needs
  • Lowest Power and Area in the industry
  • Customization Services for specific applications, protocols and processes.