Wafer Space

India

Wafer Space Name and Logo

Wafer Space was founded with the ideals of providing true value in Product and Design Services to all our clients. Our world class engineering team with its intensive knowledge in Chip Design, Embedded Software and Hardware combined with our ability to execute complex turnkey projects with a steadfast focus on quality is what differentiates us.  Wafer Space has design centers in Bangalore, India and San Jose, CA, USA.  Wafer Space expertise:

 

Semiconductor

• RTL to GDSII Chip Design

• RTL Design, Design Verification, Physical Design and DFT

• Analog Design, Layout and Verification

 

Embedded Systems

• Custom Applications, Middleware, System Software

• OS: Linux, Android, Windows, RTOS

• Connectivity, Multimedia, Platform Software

• ARM, PIC, TI, Freescale

• BSP, BIOS, Drivers and Kernel Software

• Application and GUI Development

• Firmware Upgrades, Customization, Integration and Porting

Services

Design and Verification

Areas of Expertise

  • RTL Design of IP’s, Bridges, Glue Logic
  • RTL Integration for Sub-Systems and SOC’s
  • Architecting complex test benches using OVM, VMM and UVM
  • Test planning and scheduling using coverage driven methods
  • Verification from test plan to closure using functional coverage and code coverage
  • Scoping and planning out complex projects
  • Combining Simulation and static formal verification
  • Project management of complete projects
  • System Verilog, Specman, Verilog, VHDL
  • SystemC, C, C++
  • UVM, OVM, VMM, eRM
  • OVL, PSL, System Verilog Assertions
  • PCI, PCIE, Ethernet, USB 1.1, USB 2.0, OTG, SATA, AMBA, 802.11, OCP, RapidIO, SRIO, DDR, DDR2

Languages and Methodologies

  • System Verilog, Specman, Verilog, VHDL
  • SystemC, C, C++
  • UVM, OVM, VMM, eRM
  • OVL, PSL, System Verilog Assertions

 

Protocols

  • PCI, PCIE, Ethernet, USB 1.1, USB 2.0, OTG, SATA, AMBA, 802.11, OCP, RapidIO, SRIO, DDR, DDR2
  • Many other proprietary protocols

Physical Implementation

At Wafer Space, we implement the best semiconductor chip design solution for each customer utilizing our experience and broad knowledge with EDA tools, methodologies, libraries and foundries. We have the expertise to implement projects using tools from Synopsys, Cadence, Mentor Graphics and others. Our team has the necessary expertise to implement full projects from RTL to GDSII on a turnkey or T&M basis.

 

Areas of Expertise

  • SoC Level Implementation from RTL-GDSII
  • Full Hierarchical Design
  • Full Flat design
  • Semi-Hierarchical Design
  • Mixed Signal Design
  • IP Hardening
  • High-end Flow & Methodology Development, Project Management and Program Management
  • IO Ring Planning, IO Ring Implementation, Ball Map Planning, Package
  • 14nm, 16nm, 20nm, 28nm, 32nm, 40 / 45nm, 65nm, 90nm, 110nm, 130nm, 180nm
  • Advanced Prototyping Flow
  • Full Semi Hierarchical design Partitioning Flow
  • Low Power physical implementation Flow
  • Multi-Power Islands, Multi-Voltage Islands, Multi-Vt, Multi-Level Clock Gating etc.
  • High Performance implementation Flow
  • Multi-mode Multi-corner Clock Tree expansion & timing closure implementation
  • Ultra-Low Clock Latency & Skew balancing implementation
  • OCV and AOCV based timing closure implementation
  • Signal Integrity aware implementation
  • Low Power / High Performance Verification Flows
  • Low Power physical implementation Flow
  • Static/Dynamic IR Drop, Voltage Ramp-up, MMMC Power Analysis
  • CDC ( Clock Domain Cross-over ) Analysis, Spyglass Analysis
  • UPF/CPF Based Implementation/Verification Flows
  • Timing Constraints generation / optimization from scratch
  • Physical Verification including DFM analysis /closure flows
  • Synopsys Based Design Flows
  • Cadence Based Design Flows

Technology Nodes

  • 14nm, 16nm, 20nm, 28nm, 32nm, 40 / 45nm, 65nm, 90nm, 110nm, 130nm, 180nm

Flows and Methodology

  • Advanced Prototyping Flow
  • Full Semi Hierarchical design Partitioning Flow
  • Low Power physical implementation Flow
  • Multi-Power Islands, Multi-Voltage Islands, Multi-Vt, Multi-Level Clock Gating etc.
  • High Performance implementation Flow
  • Multi-mode Multi-corner Clock Tree expansion & timing closure implementation
  • Ultra-Low Clock Latency & Skew balancing implementation
  • OCV and AOCV based timing closure implementation
  • Signal Integrity aware implementation
  • Low Power / High Performance Verification Flows
  • Low Power physical implementation Flow
  • Static/Dynamic IR Drop, Voltage Ramp-up, MMMC Power Analysis
  • CDC ( Clock Domain Cross-over ) Analysis, Spyglass Analysis
  • UPF/CPF Based Implementation/Verification Flows
  • Timing Constraints generation / optimization from scratch
  • Physical Verification including DFM analysis /closure flows

EDA Tool Expertise

  • Synopsys Based Design Flows
  • Cadence Based Design Flows
  • Mentor Graphics Based Design Flows

VIP Development

Wafer Space has the knowledge and experience to build VIP’s for any protocol. We have the past experience working in core VIP teams and can architect complete VIP’s as a product including building the core, licensing, logging and others.

 

Areas of Expertise

  • Architecture of complete VIP as a product
  • OVM, VMM based VIP
  • Verilog based VIP
  • Custom VIP interfaces for design and verification teams
  • PCI, PCIE
  • Ethernet
  • USB 1.1, USB 2.O, OTG
  • SATA
  • AMBA
  • 802.11
  • OCP
  • Rapid IO
  • SRIO
  • DDR, DDR2

Protocols

  • PCI, PCIE
  • Ethernet
  • USB 1.1, USB 2.O, OTG
  • SATA
  • AMBA
  • 802.11
  • OCP
  • Rapid IO
  • SRIO
  • DDR, DDR2
  • Many other proprietary protocols

Embedded Systems

Wafer Space provides product engineering services to multiple Tier 1 Semiconductor companies and Device makers. Wafer Space has a proven track record in product development and sustenance in the domains of Automotive, Consumer, Multimedia, Connectivity and Wireless. Wafer Space’s goal is to provide true value addition offerings to OEM’s and help create differentiated products for our customers.

 

The Wafer Space Embedded team is equipped with the domain expertise to deliver solutions for multiple segments. In Consumer Electronics we have the expertise in digital media, infotainment and connected devices. In Industrial Electronics our Engineering team is differentiated by their experience in the design and development of quality products for M2M, Machine Vision and Enterprise Networking products. In the Wireless and Data Networking space, Wafer Space team brings insights into development of 2G, 3G and LTE mobile handsets, short range wireless devices, home gateway solutions and testing of enterprise routers and switches.

 

Domains

  • Networking
  • Wireless
  • Automotive
  • Industrial
  • System Software

Services

  • System Software
    • BSP, Board bring-up
    • BIOS, Kernel customization
    • Drivers, Firmware
    • OS porting, integration and customization
    • Android, Linux, Windows, RTOS
  • System Design
    • Circuit design, Board design
    • Prototyping
    • Production ownership
  • Domain Specific
    • Frameworks, Multimedia, Connectivity
    • Android, Windows, Custom applications