The Right Process For Verification IP Development

September 24, 2014, anysilicon

This is a guest post by Arrow Devices, that provides high-quality Design & Verification products and services for ASIC/SOC. 

Verification plays a major role in any chip design project. Within that, functional verification takes lion’s share of any design cycle, 70% by some estimates. Functional verification completeness is extremely critical. Following the wrong process for developing verification IP can cause you to miss verifying some features. This can cause chip failure and cost the company millions of dollars. It has been noted that close to 70% of chip re-spins are typically due to functional bugs although that percentage has come down to ~50% in recent times. Thus following a good process with lots of planning is essential for development of world class verification IP.


Don’t “Methodologies” already exist?

Standard verification methodologies such as VMM, OVM and UVM mostly focus on the test bench building methodology rather than the process of building a complete Verification IP. Although there have been attempts to standardize the process of the building Verification IPs but they have been in there early stages. Hence there is need for a more complete methodology approach towards building Verification IPs.


So what’s the right process for developing a Verification IP? Is there any?

Yes there is! And we call it CVM – Comprehensive Verification Methodology. So here we are sharing with you what we think is the right process one should follow to come up with best-in-class Verification IPs


Continue reading the article on Arrow Devices blog