July 12, 2012, anysilicon
Walking through IKEA’s never-ending corridors you must have been seeing IKEA’s quality tests performed right in front of you. Sometimes it’s a chair being pushed by a powerful robotic arm or a drawer being opened and closed in an infinite loop with a 5.5kg sand bag inside.
Every product has a required quality level. If the quality level is not sufficient, customers will never come back for their next purchase. Or they might come back with complains asking for their money back.
Often high quality products linked to high price and vice versa, we often believe that low price goods are achieved by reduced quality level. This is not necessarily true and IKEA just want to show they keep the high standards. Their products will last forever.
I was so inspired by IKEA’s product testing, that I thought it might be a good idea to start off with a small introduction to semiconductor qualification. Not too heavy, but enough to cover the tip of the iceberg.
Once your ASIC is produced, there are specific quality tests to be performed. As a supplier, you should maintain acceptable quality level of your products, and you will need to show those test results to your customers. Just like IKEA.
Fabless vendors that sell ASICs are required to provide some documentation to prove they have done proper quality tests. For system companies that develop their own ASIC, some of the quality tests are usually done in system level, thus some of the ASIC quality test will be covered during the system tests.
JEDEC (www.jedec.org) Joint Electron Devices Engineering Council was founded just before 1960 as an independent standardization body.
JEDEC is the organization that creates the standards for all the semiconductor related material and products. They are also defining the procedure for ASIC qualification. JEDEC consists of members from the industry which contributes continuously with regards to various specifications.
This specification is the most important standard related to ASIC qualification. It is Stress-Test-Driven Qualification of Integrated Circuits which includes all the necessary tests in order to past JEDEC 47.
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
JEDEC 47 is also acting as an “top level” document and hence includes additional standards underneath. It includes the following standards:
In the next chapters we will begin our exploration of the ASIC qualification process, concentrating mainly on the JEDEC standards with some very practical tips to save you time and money. Stay tuned.
Please be advised, these standards are copyrighted by JEDEC and may not be reproduced without permission. Use JEDEC’s website to get access to the specifications legally.