Monthly Archives: July 2012

5 Easy Steps to Calculate ASIC Unit Cost

It happened to all of us. You come to your office one morning and find a note from your manager “what will be the ASIC’s unit cost?”

Although an ASIC unit cost has a direct impact on revenues, it is typically only visited twice: before the design starts and when design ends. It’s also interesting to note that ASIC cost tends to escalate during development phase. Which probably means, you need to run your calculations more often.

Here are 5 easy steps for calculating the final ASIC unit cost of your project.

The model I show here is a simplified version of the one we are using. There are more details related to ASIC manufacturing price to be taken into account, such as minimum order value, wafer-level yield etc. But for now, these are ignored. They will be covered in one of the next posts together with a neat and handy Excel ASIC price calculator.

Step 1:

Get the wafer price.

Find the number of dies per wafer.

Step 2:

Get the package price.

Step 3:

Find the test cost (both wafer test and package test)

Step 4:

Find the logistics and shipping price.

Step 5:

Guesstimate the yield.





Here is an example:

Wafer price: 2000$

DPW: 1000

QFN Package price: 0.2$

Test price: 0.3$

Logistics price: 0.1$

Yield: 90%


Final ASIC cost: 2.889$

What has IKEA to do with Chip Qualifications based on JEDEC Standards?

Walking through IKEA’s never-ending corridors you must have been seeing IKEA’s quality tests performed right in front of you. Sometimes it’s a chair being pushed by a powerful robotic arm or a drawer being opened and closed in an infinite loop with a 5.5kg sand bag inside.


Why is IKEA showing off its quality tests?

Every product has a required quality level. If the quality level is not sufficient, customers will never come back for their next purchase. Or they might come back with complains asking for their money back.

Often high quality products linked to high price and vice versa, we often believe that low price goods are achieved by reduced quality level.  This is not necessarily true and IKEA just want to show they keep the high standards. Their products will last forever.

I was so inspired by IKEA’s product testing, that I thought it might be a good idea to start off with a small introduction to semiconductor qualification. Not too heavy, but enough to cover the tip of the iceberg.

Once your ASIC is produced, there are specific quality tests to be performed. As a supplier, you should maintain acceptable quality level of your products, and you will need to show those test results to your customers. Just like IKEA.

Fabless vendors that sell ASICs are required to provide some documentation to prove they have done proper quality tests. For system companies that develop their own ASIC, some of the quality tests are usually done in system level, thus some of the ASIC quality test will be covered during the system tests.


What is JEDEC?

JEDEC ( Joint Electron Devices Engineering Council was founded just before 1960 as an independent standardization body.

JEDEC is the organization that creates the standards for all the semiconductor related material and products. They are also defining the procedure for ASIC qualification. JEDEC consists of members from the industry which contributes continuously with regards to various specifications.

JEDEC Std. No. 47

This specification is the most important standard related to ASIC qualification. It is Stress-Test-Driven Qualification of Integrated Circuits which includes all the necessary tests in order to past JEDEC 47.

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

JEDEC 47 is also acting as an “top level” document and hence includes additional standards underneath. It includes the following standards:

In the next chapters we will begin our exploration of the ASIC qualification process, concentrating mainly on the JEDEC standards with some very practical tips to save you time and money. Stay tuned.

Please be advised, these standards are copyrighted by JEDEC and may not be reproduced without permission. Use JEDEC’s website to get access to the specifications legally.


What Are The Top 3 Recommended Chip Package Types Today?

If you are debating which package type would fit best to your ASIC project, perhaps this article can help you narrow down the various options. In the semiconductor industry today there are three types of packages recommended for new designs:


Quad Flat No Leads. These are SMT packages, which consist of lead frame and wire bonding. The package consists of a paddle in the bottom to provide better grounding and heat transfer towards the PCB.

Some of the different assembly vendors are using different names for the same product.



Ball Grid Array. These are also SMT packages, which consist of a substrate (PCB) and can utilize either wirebond or bumping technologies. A BGA can provide more interconnect pins than a QFN and can dissipate more power.



Chip Scale Package. Sometimes called Wafer Level Package. These are solution targets a small size application (e.g. mobile phones) the physical size of the package is equal to or near the die size.


New Tech

For complex SOC, there are upcoming solutions which are called 3D packages.

We’ll elaborate more about these packages to help you better understand the technical and commercial benefits and drawback. Stay tuned.

foundries chart

The Chart they don’t sant you to see

Foundry business is doing good, the semiconductor market is growing and there is a continues need for silicon component supply.

While we are aware of TSMC’s market leadership, and we follow foundry ranking data every year, there is no yet an overview of the last 10 years history. What actually happened in the last decade?

Well, I have been doing an intensive research, collecting market data, drinking a lot of coffee and struggling with Excel. And the output is shown in the following two charts. The charts describe the revenues per foundry and not absolute market position. This will help us see the actual sales revenues among the top 10 foundries because the gap is extremely important for this research.

Personally, my mind was totally blown away.

One can imagine from the below diagram that TSMC really needs its own scale. It seems that TSMC has captured  so much market share while both UMC and GLOBALFOUNDRIES are trying the break the 4M$ barrier. And rest of the top 10 foundries are just well below 2M$.

Foundry Ranking

Zooming in into the 4M$ market, we can see GLOBALFOUNDRIES is doing significant efforts to close the gap to UMC.  The EMEA region has two players from top 10: TowerJazz (Israel) and XFAB (Germany). It’s very positive to see that 2 EMEA fabs are taking part in the top 10 semiconductor list.


Foundry ranking 

If you had any doubts about TSMC leadership, they’re probably gone now. TSMC will continue to grow and dominate the market. Long live TSMC.