Monthly Archives: August 2012

growth

Semiconductor Foundries Growth 2002-2012

Update (August 2012): Our internal analysis shows GLOBALFOUNDRIES to become the second largest foundry worldwide and managed to break the 4B$ barrier. See below updated charts.

Foundry business is doing well, the semiconductor market is growing and there is a continues need for silicon component supply.

While we are aware of TSMC’s market leadership, and we follow foundry ranking data every year, there is no yet an overview of the last 10 years history. What actually happened in the last decade?

Well, I have been doing an intensive research, collecting market data, drinking a lot of coffee and struggling with Excel. And the output is shown in the following two charts. The charts describe the revenues per foundry and not absolute market position. This will help us see the actual sales revenues among the top 10 foundries because the gap is extremely important for this research.

Personally, my mind was totally blown away.

One can imagine from the below diagram that TSMC really needs its own scale. It seems that TSMC has captured  so much market share while both UMC and GLOBALFOUNDRIES were trying the cross the 4B$ barrier. And rest of the top 10 foundries are just well below 2M$.

 

Zooming in into the 4M$ market, we can see GLOBALFOUNDRIES efforts payed off very well and it’s now ranked #2.  The EMEA region has two players from top 10: TowerJazz (Israel) and XFAB (Germany). It’s very positive to see that 2 EMEA fabs are taking part in the top 10 semiconductor list.

 

 

If you had any doubts about TSMC leadership – there are gone now. TSMC will continue to grow and dominate the market.

Long live TSMC.

 

popcorn

Moisture Sensitivity Level and Popcorn Effect

MSL stands for Moisture Sensitivity Level. It represent the amount of time an IC can be exposed to ambient conditions and still be assembled on a PCB without being damaged.

JEDC MSL specification

When the antistatic bag is opened and the ICs are exposed to ambient conditions, the moisture in the air is trapped inside the device. This means that during the PCB assembly process (e.g. reflow) this moisture expands and can damage the device.

The standard specification is: IPC/JEDEC’s J-STD-20

Why is this YOUR problem?

Well, the good news is — it’s not your problem. It’s the PCB fabrication house problem, and they need to specify the required MSL level because they know how long the device will be outside the ESD bag before it’s assembled. This is the floor life of a device.

 

How is MSL related to Popcorn?

The popcorn effect is when the IC “pops” because the moisture inside the package expands in the reflow process. As a result of this expansion the substrate, the die, or the wirebonds could be damaged. The damage is often invisible and requires X-ray equipment to conduct a proper analysis.

 

MSL levels

Here are the allowed exposure times for MSL categories:

 

Avoiding Popcorn Effect

To avoid the popcorn effect, simply bake the devices and seal them in a hermetically sealed antistatic bag. Use a moisture indication card to ensure you devices are not turning into popcorn.

If the devices were exposed to moisture, re-bake them and assemble the devices within the allowed explosure time. The baking is driving all the moisture out of the device.

 

Bake and Dry Pack Services

Often your test partner will be able to offer bake and dry pack your ICs just after testing.

 

 

 For more information please refer to the standard: IPC/JEDEC’s J-STD-20
loadboard

Introduction to LoadBoard Design and Production

LoadBoard (LB) is a mandatory, custom made PCB, that acts as a mechanical and electrical interface between the tester (ATE) and the device under test (DUT). LoadBoard has well-defined physical dimensions and it must fit perfectly into the tester.  It is one piece of the entire ASIC Test Solution and it should be specified in the ASIC Test Specification Document. The image shows a Loadboard with a Socket and a Stiffener.

Generally speaking, a LB consists of 2 interfaces: One interface is upwards to the tester’s handler unit. The hander is an automatic pick and place unit that takes the DUT from the tray and place it into the socket. The second interface is downwards to the tester’s pogo pins. These are the tester IO ports that electrically connect the tester to the DUT.

 

LoadBoard Properties

A properly designed LB is electronically “invisible”, and does not introduce any distortion or delay to the DUT signals. The LoadBoard should be able to support all the tests executed on the tester and be flexible enough to support future testing (for example expanding the test solution to support quad parallel testing).

In fact, many test engineers try to avoid having any active components on the LB but rather have only the necessary passive components to support the ASIC functionality. The trend of simplifying the LoadBoard is coming from need to decrease the probability of failure in production phase that can stop production line. The time of fixing a bug increases when the LoadBoard is complex.

Different testers (ATEs) require different LB size. But they all LoadBoards consist of the same elements:

  1. Socket for the DUT ASIC
  2. Interface pads for the tester
  3. Stiffener  – adding mechanical strength
  4. Some components per DUT requirements (R, C, etc)
  5. Connectors for the debug phase

In some cases, in addition of being an interface board the LB can also contain on board testing capabilities (e.g. such as FPGA). When the tester alone cannot support some specific testing task these could be performed directly on the LB (such as loopbacks).

Design rules for LoadBoard

Almost any layout or PCB engineer can design a LoadBoard, there are no special requirements besides the general understanding of the test and LoadBoard concept. A LB is typically made of RF4 material and normally very thick and consist of 20 layers or more.

LoadBoard design consideration are similar to any other PCB. Power supply distribution, clock signals routing , high speed signals routing, signal integrity, wire length all this design rules applies here too. In some cases, it’s sensible to run some electrical simulation, especially to ensure RF signal performance.

The next phase after layout is successively completed is of course manufacturing/fabrication of the board services and assembly of the board with the various passive or active components and socket.

We always recommend building 2 boards instead of just one because we use the 2nd board as a backup in case there is a failure in the 1st board. These type of failures can stop an entire production line, therefore to lower the risk of delays in production and shipping you may want to consider having a backup LoadBoard. LoadBoard fabrication and assembly could take up to 8-10 weeks depending on the design complexity.

 

Loadboard is an essential part of the ASIC test solution. Make a robust but yet simple design to ensure minimum production problems, keep one board as a backup if you can afford it.