Lock-Up Latch: Implication on Timing

December 05, 2013, anysilicon

This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.

Lock-Up Latches are important elements for STA engineer while closing timing on their DFT Modes: particularly the hold timing closure of the Shift Mode. While shifting, the scan chains

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