Monthly Archives: November 2014

TSV Integration is Creating Growth

“The long term growth of the equipment & materials business will be supported by the expansion of 3D TSV stack platforms” says Yole (Yole Développement) in its latest report, “Equipment & Materials for 3DIC & WLP Applications“. The market research and strategy consulting company, Yole proposes a deep analysis of the equipment & materials market for 3DIC & WLP applications. Under this new report, analysts announce a market multiplied by 2.5 in the next 5 years…
Equipment & Materials for 3DIC & WLP Applications report presents an overview of the main equipment and materials used in the 3D & WLP applications. Under this technology & market analysis, Yole’s analysts describe insights on a number of equipment tools, breakdown by wafer size & revenue, by type of equipment & materials and advanced packaging applications. Moreover, they also provide a detailed analysis dedicated to key suppliers, market shares and technological highlights that impact the 3D & WLP industry. Equipment & materials market forecasts are calculated from 2013 to 2019.
“Mainly supported today by flip-chip wafer bumping, the equipment market generated revenue of more than $930M in 2013” announces Amandine Pizzagalli, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing, Yole“It is expected that this equipment market revenue will peak at almost $2.5B”, she adds. This market is fueled by the 3D IC technology with TSV interconnects, an area offering opportunities for new developments in equipment modification— equipment that is much more expensive than the tools used for established Advanced Packaging platforms :3D WLP, WLCSP and flip-chip wafer bumping. Indeed, according to Yole, 2015 will be the key turning point for the adoption of 3D TSV Stacks since the memory manufacturers, such as Samsung, SK Hynix, Micron, have already started to ship prototypes this year and might be ready to enter in high-volume manufacturing next year.



In its latest announcement (Source: Song Jung-a, Financial Times), Samsung Electronics reveals its $14.7 billion investment, to build a new semiconductor plant in South Korea. This investment becomes the biggest single expenditure on a memory chip factory.


According to the Korean company, construction of the world’s biggest plant will begin in the first half of next year and complete in the second half of 2017. In addition, logic manufacturers will diversify investments from System-on-Chip to Package-on-Package and will benefit from Advanced Packaging platforms such as 2.5D interposer and FOWLP to stimulate their high-volume production.


From the materials side, Yole confirms: “The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%”. Growth will mainly be driven by the expansion of the next generation Wafer-Level-Packaging platforms: 3D TSV stacked memories, multi-layer RDL for FOWLP & WLCSP. Such platforms are becoming more complex and requiring additional and various thin layers, as well as advanced materials, to achieve better performance.


More information about Advanced Packaging reports is available on



This is a guest post by Yole Développement that provides marketing, technology and strategy consulting.

stacked wafers

The Macroeconimics of 450mm Wafers

SEMICON West 2014 in San Francisco was a great place to meet bloggers in the semiconductor industry to get updated on the status of 450mm diameter silicon wafers. On one side, there is a good news about the unprecedented level of collaboration taking place between the design and construction professionals through the Global 450mm Consortium (G450C) to deconstruct a semiconductor facility matter associated with 450mm adoption. But on the other hand, the transition to 450mm seems delayed till 2020 with Intel and TSMC backing off their timing for introduction of 450mm in volume production.


An analysis of the macroeconomics of this capital intensive microelectronics business and its impact to macroeconomic growth of U.S. economy shows that 450mm diameter silicon wafers need to be introduced sooner rather than later to keep this business profitable and for sustaining the macroeconomic growth. This article presents an analysis of the macroeconomics of manufacturing 450mm diameter wafers, how it would help in sustaining progress of Moore’s Law and what precautions need to be adopted by semiconductor industry at G450C to ensure a sustainability of huge capital investments for transitioning to 450mm diameter wafers.


The global semiconductor industry has been constantly increasing the diameter of the silicon wafers it uses to reduce its manufacturing costs through mass production. The larger the diameter of wafers, the more real estate of silicon that is available for manufacturing. The increasing process complexities in nanoscale engineering add to silicon manufacturing costs. However, if the percentage increase in manufacturing costs per wafer from advancements in technology is smaller than percentage increase in revenue from the larger real estate of silicon, then the semiconductor manufacturing business becomes profitable.


At present, the semiconductor industry is widely making use of 300mm diameter wafers, and there is some progress towards 450mm diameter wafers, but major players are delaying their investments for 450mm diameter wafers due to significantly high manufacturing costs of semiconductor processing tools and lower expected returns on investments. The major players in this business do not expect to reap significant returns from their huge capital investments which is raising questions whether mass production of 450mm diameter wafers would even become a reality anytime in near future.



Whenever a new wafer size is first introduced, the cost per square inch of silicon on a given wafer size is at its peak. But, as the technology matures, this cost per square inch drops with time. The minimum silicon cost reached with 125mm diameter wafers is about US$ 1 per square inch. The minimum silicon cost with 200mm diameter wafers is about $2 per square inch, resulting in a maximum cost per wafer of $100.. The minimum silicon cost reached with 300mm diameter wafers is about $3 per square inch, resulting in a maximum cost per wafer to of $400. Thus, for every succeeding increase in wafer size, there is approximately a 1.4 times increase in costs of manufacturing.


The silicon wafers that are used for manufacture are sliced from a silicon ingot, which is approximately 99.99999 percent pure silicon. The increases in cost per square inch occurs due to other reasons, such as the percentage of wafer that actually goes into the product, actual consumption of these wafers, and the research and development costs involved in the manufacture of wafers. Because of increasing processing complexities in subsequent generations of increased wafer size, the thickness of the wafers sliced from silicon ingots is larger. Thus, the total number of wafers that can be sliced from a silicon ingot decreases with increasing wafer sizes.


Additionally, the actual silicon going into the wafers is a small percentage of the total silicon available for use from these silicon ingots. According to Rose Associates, this percentage was 30 percent for 150mm wafers, 17 percent for 200mm wafers, and close to 10 percent for 300mm wafers. Based on this trend, the percentage of actual silicon from ingots that would go into use for 450mm wafers would be even lower than 10 percent, possibly closer to 5 percent, based on the observed trend. Thus, the actual silicon from ingots going into electronic products is progressively decreasing for every generation of increase in silicon wafer size. A larger wafer size also increases the number of chips that are mass produced.


The above data analysis educates us that for ensuring a sustainability of huge capital investments towards a transition to 450mm diameter wafers, the majority of silicon that is manufactured inside a semiconductor wafer fab should get consumed in the manufacture of electronic products. Now the question is how does semiconductor industry make it feasible? A good consumption of manufactured silicon can be achieved only when there is a robust economic demand for latest and greatest electronic products. Hence, the G450C consortium should not only ensure reduction in costs of manufacture to ensure sustainability of production but should also collaborate to ensure that there is good consumption of its manufactured products. This can be made possible only in an economy where the consumers have a higher purchasing capacity to generate a robust demand for semiconductor products.


The Global 450 Consortium (G450C), a New York-based public/private program with leadership from GlobalFoundries, IBM, Intel, Samsung, TSMC, and the College of Nanoscale Science and Engineering (CNSE), is housed on State University of New York’s (SUNY’s) University at Albany campus and maintains focus on 450mm process and equipment development. In this consortium, there is an unprecedented collaboration and cooperation between previous competitors in such a way that:
•All key players are coming together
•CNSE is providing a uniquely neutral and technologically advanced home for critical research
•Work of the G450C is being guided by a strict application of an inside-out design approach
•Key advances have been made in utility requirements, overhead conveyance systems, and energy efficient strategies.


This collaboration is first step forward by the global semiconductor industry to ensure a steady supply of 450mm diameter silicon wafers at a reduced cost. However, unless this consortium also ensures a similar collaboration and cooperation to generate a steady demand for this newly manufactured silicon, the huge capital investments made by the participants in the G450C consortium towards a transition to 450mm diameter silicon wafers cannot become sustainable.


On the macroeconomic side for U.S. economy, the consumer purchasing power of majority in the U.S. economy has shrunk because of the transformation of U.S. economy from a free market enterprise to monopoly capitalism. As a result of this, there is a growing gap between the wages and the productivity of employees in the U.S. and global economy, which is resulting into a loss of economic balance. When capitalism is reformed to a free market enterprise, and it works for all citizens in an economy, it would usher in an economic democracy. As it would work for all citizens, monopoly capitalism will become mass capitalism.


In order to sustain the progress of semiconductor industry which has been driven by the relentless progress of Moore’s Law, macroeconomic reforms have become critical to allow semiconductor companies to justify their ever-increasing capital-intensive investments for transitioning to 450mm diameter wafers. By establishing free markets, supply and demand of electronic goods would grow in proportion, thereby resulting in a balanced economic growth, low income taxes on individuals, higher investments, increased motivation for employees to work hard, and the growth of the overall economy. These free market reforms seems to be the only path forward for global semiconductor industry to ensure its sustainability for transition to 450mm diameter silicon wafers.


When the G450C consortium collaborates to bring about such profound macroeconomic reforms, even if the future improvements in process technology for progress of Moore’s law are less from one process generation to another, the macroeconomic growth in the overall economy would be very high. These reforms would ensure that the consumer purchasing power and hence prosperity of overall economy would be very high. With a high economic demand, the demand for the latest and greatest electronic products will continue to grow. In this way, the G450C consortium can ensure a good consumption of all manufactured silicon from larger size of 450mm diameter wafers. This robust consumer demand would force semiconductor industry to make more investments and manufacture latest and greatest electronic products to meet that growing demand.


In this way, mass capitalism based free market reforms envision sustainability of huge capital investments in the transition to 450mm diameter silicon wafers. Looking back into the history of macroeconomics, it can be observed that an economic depression might occur when money that is in the possession of individuals stops rolling. Some of major players in global semiconductor business are concerned that their investments for transitioning to 450mm diameter wafers would not give any significant returns. This could turn out to be one of the causes for money to remain inert or unutilized in this capital intensive business.


As a result of above policies, money in the economy would become immobile or inert; consequently, there would be no investment, no production, no income and hence further reduction in consumer purchasing power. The situation could become so dangerous that there would be very few buyers to buy new electronic goods. This macroeconomic analysis explains why macroeconomic reforms have become critical for transition to 450mm diameter silicon wafers to ensure that money does not remain inert and it keeps circulating in the economy in order to keep increasing the consumer demand for the latest and greatest electronic products. Without above proposed macroeconomic reforms, progress of Moore’s law seems impossible and chances of the U.S. economy transitioning from a great recession to a depression seems inevitable.



This is a guest post by Mr. Apek Mulay. He is CEO of Mulay’s Consultancy Services. He is an analyst, blogger, entrepreneur, and macro-economist in the U.S. semiconductor industry.

Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place of IP modules yet to be designed. The goal of the first model use-case is to reduce the likelihood of human error resulting in IC functional faults. The goal of the second use-case is to develop an executable specification upon which the detailed design of IP blocks may be based.



1. Introduction:

As the size and complexity of SOCs and ICs increases, the critical task of finding and eliminating human error becomes more and more difficult – even for digital-only chips. Adding analog circuitry magnifies the problem. By its very nature, analog design and verification is more complicated than digital. When the design of analog modules is outsourced, the experience can be frustrating and traumatic enough for the faint-of-heart to avoid future purchases of analog IP altogether.


1.1 Analog and Mixed-Signal IP

Some have claimed that the term “Analog IP” is an oxymoron – that providing analog circuitry in a form which can be plugged in without analysis, and adjustment is simply impossible for other than trivial analog functions. [1]

The position of the article referenced above is that using IP should be as easy as attaching a new printer to your PC. And if the delivered package requires further customization for its end application whether by the vendor or customer, it is not properly IP at all. The vendor is providing a design service.


1.2 Difficulties of Reusing Analog/M-S IP

The design flow for analog systems is not as clean as is digital system design flow. Analog design flow cannot be automated; practical circuits can’t be automatically synthesized or optimized, mostly due to the fact that analog circuit design must address many more parameters than digital design. Furthermore, analog designs in general are not portable from one technology node to another. A change in technology involves at least device resizing and often requires architecture changes. In addition, once the analog IP is ready to deliver, its successful instantiation into the target circuit is prone to human error. Each bias and reference line requires correct electrical connection. Digital controls, clocks and data must be connected and the timing interface to the analog IP must be correct. [2]


1.3 Typical Attempted Solutions

In a typical approach the analog IP provider exhaustively simulates the IP using SPICE or an equivalent circuit simulator, and provides installation specifications and requirements documentation. It is then up to the buyer to ensure correct instantiation. When the IP buyers’ best efforts fail (or they decide to reduce their risk of failure) the IP provider becomes a design service provider playing a larger role in designing the IP into the SOC. A better approach is for the IP provider to supply a behavioral model along with the documentation so the buyers can reassure themselves by seeing the IP operate in their verification environment. Questions arise regarding the quality of the behavioral models. In many cases for the sake of simplicity, execution speed, and quickly getting the verification platform up and running, the models do not accurately incorporate the functionality of every port in the IP cell. In the worst case, too simple a model can camouflage mistakes in its instantiation or control.


1.4 Efficient Use of Behavioral Models

An inaccurate model is worse than no model at all. Falsely reporting failures can delay final tape-out or cause unnecessary redesign of the target SOC. Worse than that, false optimism may allow design bugs to escape into Silicon, possibly wasting millions of dollars and months of redesign. It’s difficult to argue against model accuracy, but what about simulation time? A totally accurate PLL model may be required to verify certain functionalities, but requires mille-seconds to start up, acquire and lock. Running hundreds of regression simulations with such long run times is obviously unacceptable. The solution this paper proposes is to use multiple model views, targeted toward executing each testcase of the verification plan with no more than adequate accuracy.


1.5 Overview of Following Sections

The remainder of this paper discusses the following topics. Section 2 describes the concept of using multiple model styles or views, and choosing from the collection of styles to optimize speed versus required accuracy for efficient simulations. Section 3 discusses the use of behavioral models to prototype an SOC, describing a top-down design methodology, using behavioral models as an executable specification when designing or purchasing analog IP and using behavioral models to enable reuse of existing analog IP. Section 4 deals with efficient verification of mixed signal SOCs, from developing a verification plan (V-Plan), to creating testcases, to choosing model views for each testcase. A partial V-plan is developed for a hypothetical SOC, and model view choices made for several testcases. Section 5 talks about two approaches managing the various model views and how the choice of one view over another is made at simulation run time, whether manually or as part of a regression script. Conclusions are summarized in section 6.


2. Multiple, Targeted Model Views

Fundamentally there is a trade-off between model accuracy and model execution speed. The next paragraphs talk about various model levels and their appropriate use.


2.1 Fully Electrical

These have the highest level of detail but slowest execution. May be written in Verilog-A, Verilog-AMS or VHDL-AMS, the fully electrical model view is compatible with device-level netlists (transistors). Verilog-A models are executable in SPICE-like simulation environments such as Spectre, H-Spice and Eldo. All Verilog-A I/O and internal nodes must be electrical in nature, even those of digital functionality. Verilog-AMS and VHDL-AMS may only be run in AMS simulators such as Cadence’s AMS Designer and Mentor’s Advance AMS. Fully Electrical models are the most detailed and exhibit conservation of charge on all electrical I/O and internal nodes. (The AMS languages include the possibility of digital I/O and internal nodes which are described behaviorally). The circuit is described in terms of voltage and current flow. Generally unsuitable for SOC verification, fully electrical models are valuable in top-down design flows and in verification of analog sub-systems.


2.2 Behavioral Electrical

These have less detail but execute faster than fully electrical models. Written in Verilog-AMS or VHDL-AMS, these models describe analog behavior in terms of algebraic and differential equations rather than voltage and current. Their electrical I/O exhibit conservation of charge but internal functional behavior is described by real variables wherever possible. Behavior may be as accurate as required by skewing the modeling style toward the Fully Electrical behavior. This level of model is the most suitable for detailed SOC verification of the interface, timing and control of the collection of analog IP blocks in their entirety.


2.3 Signal Flow, with or without Electrical Behavior

These have less detail than the two preceding styles and execute much faster. This model style may be written in plain digital VHDL or in Verilog-AMS. The signal path through the model avoids the use of an analog circuit solver. It combines event-driven and self-timed analysis and executes simple mathematical processing of the signal. Verilog-AMS and VHDL-AMS models can use this approach while simultaneously using an electrical approach to monitor bias currents and reference voltages. Plain VHDL (without electrical behavior) can use the signal flow approach without requiring the AMS language extension. Plain digital Verilog has no concept of real wires or ports, but Verilog-AMS includes ports and wires of type wreal (for wire-real). There is no feedback path in this style of modeling, and there is no analog solver to choose the sampling points. Op-amps along with their feedback network are replaced by gain blocks. A built in sampling plan must be written into the model which obeys the Nyquist criteria. As one might expect, this style of model executes blazingly fast and is the top choice for verifying the full SOC signal path including the analog section. Modeling the signal path using reals (or wreals) and using electrical modeling techniques for the bias and reference network, results in a nice combination of verification coverage and high execution speed.


2.4 Plain Digital Equivalent

Written in plain digital Verilog, these are the fastest of all Verilog models. Since Verilog doesn’t allow real nets or ports, a rather tedious but rewarding workaround uses out-of-module references (OOMRs) to pass signals from one digitally-modeled analog block to the next all the way from the input source to the A/D converter. It must be assumed that connectivity and bias integrity are verified in other testcases using more accurate models. This model type is suitable for simulating an extensive digital section of the SOC along with the analog front end.


2.5 Base-band Equivalent Models for RF

Verifying an SOC’s instantiation of RF IP blocks should not require verifying the RF IP itself. That is best left to specialized RF simulators. As in the PLL example, a very few testcases may require accurate wide-band models of the RF IP blocks. For the bulk of full chip verification it is often acceptable to use base-band equivalent models. In these models of the PLL, Signal Source, LNA, Filter and Mixer, the positive/negative paths are replaced by I/Q paths. A frequency variable is passed by OOMR from the behavioral PLL model to the other RF blocks. The models are written to verify the correct PLL frequency and correct biasing and control but execute much faster than wide band models which would be required to operate at greater than twice the carrier frequency.


3. Prototyping with AMS Models

Ken Kundert points out “The key to improve analog design productivity and efficiency lies in the ability of the design organization to be able to develop and deploy a ‘systematic design methodology’, not in tool automation alone.” [3] This section describes a prototyping methodology using behavioral models which then act as an executable specification for the analog IP to be developed.


3.1 Mixed-signal Methodology

Figure 1 shows the flow chart of a top-down mixed-signal design methodology incorporating a prototyping phase using behavioral models of intellectual property yet to be designed. The prototyping phase begins at the point marked “A” and ends at point “B”. At “A”, an architectural-level model has been created using Matlab, the C language or some other high level modeling language and simulation tool, and accepted by manually inspecting and comparing to requirements. It is then a manual task to translate the high-level model into digital and analog behavioral models and integrate them into a top-level module and test bench. This test bench must be simulated and its behavior manually compared to that of the architectural level model.


As to the choice of model styles to use in the prototyping stage, begin with the all-digital equivalent described in 2.4. Compare the behavior to that of the architectural-level simulation, and then evolve the model into the signal flow type described in 2.3. Once accepted (at point “B”), the model prototypes evolve further to become executable design specifications.


Figure 1: Top-Down Mixed-Signal Design Flow


Unlike the manual comparison between the prototype and the architectural level simulation, from point “B” forward the “real” design can be substituted and simulated in whole or in part for the prototype behavioral models. From point “B” there is a well known and mature design and verification flow for the modules comprising the digital portion of the IC.


For top-down analog module design flow, each behavioral model used in the prototyping phase is instantiated into its own testbench along with a stimulus driver and stimuli waveforms created to generate all the required analog behavior. Fully electrical models using Verilog-A as described in section 2.1 or behavioral electrical models as in section 2.2 are provided to the analog design team. Detailed analog design may continue and AMS simulations run on platforms such as Cadence’s Analog Design Environment (ADE) or Mentor Graphics’ Advance AMS.


This package serves for both specification and model validation. The initial model versions might only include signal I/O and control. The transistor-level design will require power supplies, reference voltages and bias currents. As these are added to the schematic and symbol, the model and the stimulus driver are revised to include the actual pin-out. The model behavior is refined to match the circuit’s behavior. As the analog block design is completed, and the final refinements are made to the model, the top-level testbench is also modified to fit the final analog block. The final full-chip behavior must again be verified versus the accepted architectural-level behavior.


Successful functional verification is the final step before tape-out and is discussed in section 4.


3.2 IP Purchase and Reuse

Two important use cases are the purchase and reuse of IP. The behavioral model prototypes once accepted at point “B” and packaged with a testbench and set of stimuli as described above may become part of the requirements document when purchasing digital or analog IP from a vendor. Conversely, when one has IP on hand from a previous project using this flow, use its behavioral models in the prototyping phase.


4. Verification with AMS Models:

The starting point for efficient verification is the Specification Document, from which a Verification Plan Document (V-Plan) is developed. The V-Plan includes a list of testcases which when successfully executed verifies all of the device specifications are properly designed. Each test case implies a certain degree of model accuracy on the part of the models of the analog IP.


4.1 Specific Example

Figure 2 is an iconic diagram of an RF mixed signal SOC showing

  • Analog-to-digital, digital-to-analog and RF down-conversion paths
  • Other analog functional blocks
  • Digital modules to calibrate and control the analog functional blocks
  • Other digital functional blocks


Figure 2: A Mixed-Signal SOC Diagram

Some of the testcase categories for a representative V-plan appear in Table 1.

Table 1: Partial V-Plan Categories


Taking a PLL model as an example, one or a few testcases in the Calibration or Control categories might require a Behavioral Electrical view which exhibits detailed and accurate (but slow-executing) analog behavior such as frequency acquisition and phase lock. A few testcases in the Signal Variants category may require less detail, possibly a model which exhibits an idealized transition between frequencies. A Signal Flow model would be an adequate choice. Maybe 99% of the SOC testcases do not focus on the PLL at all. For most Signal Variants and all Digital Functional testcases a Plain Digital Equivalent is the fastest choice and is perfectly adequate.

The bottom line requirement is to fulfill the Verification Plan as efficiently as possible. If highly accurate models are used in all testcases, regression simulations will require an unacceptably long time. Not enough accuracy will result in coverage holes and risk of faulty Silicon. Choosing from a variety of model views can cover the entire V-Plan in a patchwork manner in a reasonable amount of time.


5. Managing Model Views

The case for requiring several model view types has been presented, but how are the view types chosen and compiled into the simulation database? Two methods exist.

Taking a PLL model as an example, one or a few testcases in the Calibration or Control categories might require a Behavioral Electrical view which exhibits detailed and accurate (but slow-executing) analog behavior such as frequency acquisition and phase lock. A few testcases in the Signal Variants category may require less detail, possibly a model which exhibits an idealized transition between frequencies. A Signal Flow model would be an adequate choice. Maybe 99% of the SOC testcases do not focus on the PLL at all. For most Signal Variants and all Digital Functional testcases a Plain Digital Equivalent is the fastest choice and is perfectly adequate.


The bottom line requirement is to fulfill the Verification Plan as efficiently as possible. If highly accurate models are used in all testcases, regression simulations will require an unacceptably long time. Not enough accuracy will result in coverage holes and risk of faulty Silicon. Choosing from a variety of model views can cover the entire V-Plan in a patchwork manner in a reasonable amount of time.


5. Managing Model Views

The case for requiring several model view types has been presented, but how are the view types chosen and compiled into the simulation database? Two methods exist.

`ifdef Beh_Elec
//… Beh_Elec Model Code
`elseif Sig_Flow
//… Sig_Flow Model Code
//… Dig_Eq Model Code



6. Summary and Conclusions:

This paper presented the case for requiring and using multiple model views or styles of analog behavioral models, and how to take advantage of each style of model to improve the quality and efficiency of SOC prototyping and verification. Taking the time to set up a top-down design methodology followed by a well-planned bottom-up verification methodology can improve the chances of first-time Silicon success and faster time to market.




[1] “Analog IP business not likely soon, say DAC panelists”, Richard Goering, EE Times,

[2] Reference: “An Analog Verification and IP Development Environment”, Stephan Weber, Cadence VCAD, D&R Industry Articles

[3] “When Will the Analog Design Flow Catch Up with Digital Methodology? (Panel Session),” dac, pp.419, 38th Conference on Design Automation (DAC’01), 2001


This is a guest post by Robert Peruzzi, Ph. D. — R. Peruzzi Consulting, Inc

What Does It Cost You When Your SoC is Late to Market?

If your chip is late to market, it is costing you far more than you know.


Arteris conducted a survey of all its chip design customers to gain a more accurate grasp of the major concerns they have in their day-to-day operations and to gain a better understanding of what drives their decision making.


It is no surprise that time to market is one of the biggest concerns. The category that we call “Often late or slip” registered as a top design challenge to about 11 percent of the customers responding. Many of us here are quite surprised that this percentage isn’t higher.


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Figure 1. Arteris recently conducted a survey of its customers top design concerns. ‘Often late or slip’ ranks as one of the key challenges. (Source: Arteris)


We think those who carefully consider the consequences of schedule slips have taken proactive steps to get to market on time or early. These same companies are taking market share in emerging, high-growth product categories, and they are getting design wins in time for the critical seasonal product cycles. That’s why these same companies place a priority on efficient execution. In our dealings with multiple customers, we’ve discovered companies that invest up-front in time to market wind up increasing their design starts. It’s no coincidence that many of these same companies also achieve volume leadership.

Time-to-Market Underscores All Aspects of Chip Design

Power, performance and area concerns dominate most chip development and those costs are easy to quantify.


In our survey, 14 percent of our respondents said reaching design frequencies is a top design challenge and 13 percent said that low-power requirements were the most important.


When 11 percent of survey respondents indicate that debugging designs is a major challenge, or that complexity struggles represent 10 percent of top concerns, what this really indicatesis that time to market is the underlying cause.


Even when 10 percent say back end routing is a challenge, it’s clear that anything causing a chip to miss its introduction date adds to the cumulative anxiety.


Debugging designs, complexity and back-end routing can all derail time to market goals if chip design teams cannot address these challenges in an expeditious matter. Even other top concerns such as integration of third-party IP (10 percent) and the coordination of design teams (9 percent) speak to time to market.


But do chip companies really know the cost of being late? Or do they know how much pricing power they can gain by being early? We know that some companies really do understand how to calculate these costs and they are using this knowledge to execute more effectively.

Revenue, slip, equation, SoC, Design, slip, delay, late-to-market

Figure 2. Projecting the revenues over the lifetime of the SoC will be instrumental in calculating the costs of being late. (Graph: Arteris)


Calculating the Cost of Schedule Slips

There is an easy way to calculate time to market factors and the potential loss of revenue if your chip is late. Look at a product sales window of 18 months to two years, for example, and determine how much revenue the product will generate over time.  Research shows that products will reach peak revenue at the mid-point of the window. From that, companies can develop a growth curve for the introductory period and a downward slope after the market peak.


Using a formula based on proven economic research and actual industry experience, calculations show that in the case of a product with an 18-month long product sales window, companies will miss over 34 percent of product revenue if they are even three months late on introduction. To restate: If you are just one-sixth late, then you lose more than one-third of your potential revenue.


The formula for calculating the negative effects of shipping a product late to market is based on research conducted in academia, business schools and economics and it’s derived from commonly accepted principles about the technology adoption lifecycle.  The concepts used to create this formula can also be used to estimate the added revenue potential of early arrival to market. It shows how companies can gain pricing power at the expense of the competition if they launch earlier than expected.

Accelerating the Pace of Introduction

Arteris FlexNoC interconnect fabric IP is helping customers to accelerate time to market. It is helping companies integrate third-party IP at a faster rate and with greater ease. It is helping them to organize their global teams based on a hierarchy of design challenges.  FlexNoC allows chip design teams greater flexibility to respond to engineering change orders. Compared to using obsolete hybrid bus or crossbar architectures for the SoC fabric, FlexNoC is far more effective in reducing the complexity of SoC designs. It also enables faster debugging and back end routing. Because of all these reasons, using Arteris FlexNoC SoC fabric IP reduces the probability that your chip’s schedule will slip, and increases the chances that you will be able to sell your product earlier than planned.


Any global design team that seeks to gain an advantage in a critical market should be well aware of the costs of being late to market. Factoring this important information in to chip planning will drive teams to place higher priority on getting their designs out in time to capture greater revenue.



This is a guest post by Kurt Shuler, Vice President of Marketing at Arteris. Click here to learn about Arteris products.