Monthly Archives: May 2015

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Lidless BGA – Overview

Lidless BGA package essentially offers one main advantage compared to a heatspreader-BGA packages: better thermal performance. The second advantage of the lidless BGA is lower cost due to the fact that a heatspreader is not used in lidless BGA configuration. This article will cover the thermal properties of the lidless BGA package.

 

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In the lidless BGA package, exposure of the die allows for direct contact between the die and heat sink, which increases the thermal performance of the chip. While lidless BGA packages achieve better thermal performance, they present a few tricky challenges in handling because lidless BGA does not consists of a heatspreader which makes the pick and place slightly trickier.

 

Lidless BGA packages basically enable a direct die contact to an external heat sink, ensuring the lowest thermal impedance between the flip chip die and the attached heat sink. With a properly designed heat-sink and Thermal Interface Material (TIM), lidless BGA package can achieve thermal resistance values better than a lidded package.

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It is advised to select the thermal interface material (TIM) early in the design phase because  TIMs can be the limiting factors in the expense of thermal management designs. This choice depends on cost targets, package application, manufacturing dynamics, and the performance requirements of the thermal solution.

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China Jianguang to buy NXP RF Power Unit

Within the second half 2015 China Jianguang will complete the acquisition of NXP’s RF Power Unit for $1.8B. For some analysts this was a necessary strategic step as a result of the acquisition of FreeScale Semiconductor that has as well a similar unit.

 

The buyer is Jianguang Asset Management Co which is an investment company based in China. The company is a subsidiary of JIC Capital which is a state-owned investment group. JAC Capital was established for the purpose of investing in high TECH industry including Integrated Circuit and semiconductor, IT and Networking, Data service, Cloud Computing and Telecommunication.

 

The following will be transferred to a new company that will be based in the Netherlands

  1. 2,000 NXP Netherlands-based employees
  2. All IPs  and patents associated with this business unit
  3. NXP operation in the Philippines (package, assembly & test) associated with the unit

 

 

 

The semiconductor landscape is showing a slower growth that leads to a wave of mergers and acquisitions. Who do you think is next? (please comment in the area below)

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Mega Semiconductor Merger?

Avago Technologies , the Singaporean chipmaker that  started out as a division of Hewlett Packard (HP), is in advanced negotiations to acquire American chip manufacturer Broadcom, which makes chips for about half tablet computers and smartphones worldwide, its customers include Amazon, Apple, Google and Samsung , reported the newspaper “Wall Street Journal”.

Terms of the transaction were not disclosed evolving and there is no guarantee that the negotiations will mature eventually into a deal, the Journal reported.

Broadcom shares jumped 20% in trading on Wall Street, and the company’s market value jumps to $34 billion. Avago Stock increased by 10% and the company’s market value climbed to $37 billion.

Reports of the deal being worked out between Avago and Broadcom join the mergers and acquisitions that happened this year and last year in the global chip sector. Dutch semiconductor manufacturer NXP announced in April the acquisition of chip maker Freescale for 11.8 billion dollars.

 

 

A month earlier, the, “Wall Street Journal” that the chip giant Intel is negotiating the acquisition of chip maker Altera (Altera), which is traded at a market value of $14 billion. However, several weeks later, the television channel CNBC reported on the collapse of the trade talks, which if implemented would go was the biggest acquisition in the history of Intel.

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Selecting a Wedge Bonder – Tutorial

Palomar/Hughes started designing and manufacturing wedge bonders in the early 1980s for the aerospace and defense industries. Later, these machines were used for a wider array of applications beyond just military, including medical devices, RF/Wireless packages, automotive sensor systems, and optoelectronic systems and components. Ultrasonic wedge bonding was introduced in the early 1960s.

 

Automated wire bonders were first introduced nearly 40 years ago. At this time, the majority of interconnects were made using aluminum wire. As the need for high reliability increased, gold wire became more common. As package densities increased, wire interconnect bond pitches decreased. The initial solution to the fine pitch challenge was wedge bonding due to the design of the wedge tool allowing wires to be bonded in close proximity (side-by-side).

 

Throughout the years, several features have remained common among wedge bonding equipment such as wire fed through the tool and the wire clamping behind the tool. Today’s wedge bonders are vastly different from those of the past, as well as performance capabilities differing from manufacturer to manufacturer. When selecting a wedge bonder, you should consider the following criteria:

 

Criteria #1: Capability to handle gold, aluminum, and ribbon wire

Almost every wedge bonder is capable of handling all three types of wire. However, modern wedge bonders such as our 9000 Wedge Bonder, can handle all three wire types without changing the wire clamp.

 

Criteria #2: Better control on wire feed

Older wedge bonders have longer wire spans from de-spooler to wire clamp which renders poor control of the wire feed. The wire, especially ribbon wire, can easily be twisted and affect the bonding quality. The advanced wedge bonders of today have overcome such obstacles.

 

Criteria #3: Easier conversion between different wire feed angles

Older wedge bonders are designed to specifically cater to one type of wire feed angle. If you have a wedge bonder equipped with a 45-degree wire feed angle, you cannot use it for deep access bonding applications without replacing the entire bond head with a deep access wire clamp. Not only is this costly, but it is also very time consuming to change the bond head because the bonder may have to stop production for a couple of days during the conversion. The good news: modern wedge bonders have done away with bond head changes and are now capable of converting from a 45/60-degree to 90-degree wire feed.

 

 

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Criteria #4: User-friendly programming

Programming wires can become a nightmare, particularly when the number of wires runs into the hundreds and thousands. Our modern wedge bonders are now equipped with user-friendly intelligent interactive graphical interface,i2Gi®, as a standard feature which allows the management from part design and development, to process validation and finally to intuitive operations control.

 

Criteria #5: Contactless height learning saves time

Older wedge bonders use a physical contact to learn the heights of the surface to be bonded when learning or transferring programs onto a machine.

The method is slow, time-consuming, and can cause damage to the parts. However, modern wedge bonders are intelligent enough to learn the heights without

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having to make physical contact with the parts providing protection to the valuable parts.The 9000 Wedge Bonder has auto focus with part height update which is useful during production runs to better handle part height variations.

 

 

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This is a guest post by Palomar Technologies, formerly Hughes Aircraft, which is the global leader of die attach solutions, wire bonding equipment, optoelectronic packaging systems and precision assembly services.

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Debugging in System Verilog Constrained Random Verification

70 % of ASIC design goes in verification and 70 % of verification goes in debugging.

 

Planning for the debugging goes a long way. Feature by feature the way we architect the test bench pay some attention as to how will it be debugged. This strategy will pay back heavily. One old principle is don’t forget the basics. Understand the ground rules well. In verification ground rule is generate the stimulus and check the response. That’s it.

 

 

In the directed case it would be evident just by reading the test source code. The same is not true when one looks at the the CRV test benches. Although the ground rule is still the same. Well debugging the CRV test benches is little different ball game. Now one needs to figure out the stimulus  generated from the test logs. There is no source code to refer on the lines of directed case. I am not going to talk about technicals of the vmm_logs. May be I will put a word or two as to what customization can be done to make it more effective.

 

0. Usage for the Logs is they are 90 % of time grepped and not read line by line. So design the regular
expression friendly logging messages.

 

1. Just because they are grepped does not give you a license to go wild and print the universe. Follow
some good logging etiquette. Well formatted information is worth the time spent in putting up the format.
Address map, details of transactions, configurations needs be formatted to ease the read.

2. Implement intent driven logging macros. Intent driven macros could distinguish between the messages
that give out information about specification, implementation, test bench specific etc. This can help in debugging across teams. Lets look at a case where the unit test bench gets ported to system.System team might just be interested in the messages that give out the spec information and they may not be interested in the test bench specific messages. So it would be good to have this control.

 

3. With the vmm logging macros tend to print out multi line messages. Do customization to make them
single line. Also group the related multiple lines that need to go together in a string data type and print it out with the single call to messaging macro. While built in vmm component logging is useful it can be big distraction and can increase your log file sizes beyond wave dumps. So have knobs to turn off this internal logging and enable only your own TB logging or together.

 

4. It should be very straight forward to find out the stimulus generated and the response given out by the DUT. VMM test benches heavily utilize the concept of the transaction and transactor. Transaction go via
the channels. The built in logging of the channels puts out messages about transaction being added/removed.
This can be very informative for the stimulus and response extraction.

 

5. Debug messages cannot be put just for the sake of it. There needs to two views that needs balanced.
One is being able to have as complete information as possible being available in the logs when the highest
verbosity is enabled but the second one is ease of localizing the issue using a question/answer/elimination.

Few simple quick information to help ruling out the basic issues. There on eliminations. First one is : Is it

really a RTL or test bench issue. If its test bench issue then it should answer is it originating in generator, transactor, BFM, score board, driver, checker etc

 

6. For TB issues after its localized to a component put enough information to be able to figure out what is the state of different threads in the component. If its waiting for some event it will go a long way to put that debug message as to what it is waiting for.

 

7. End of test itself can be multi phased. Put enough information to indicate as to which phase of end of test is being waited on.

 

8. Even when its closed as RTL issue messages need to be clear enough to convince the designer. It should be easy enough to give the picture of scenario as designer would imagine.

 

9. Build the set of frequently used regular expressions and use the egrep to find out the complete sequence of event that took place. This bigger picture is very vital.

 

10. Have a easy mechanism to identify the requests and corresponding response. For the buses that allow
multiple outstanding requests and allows out of order completion it goes a long way to build this
identification mechanism. Even though the bus may have some id mechanism of the transactions as they get reused it might be tough to debug. Go ahead and add TB id for the transaction as well that is unique throughout the sims and map the completions on to this ID and it greatly ease the debug.

 

11. Don’t plan to debug everything using logs and thus put everything in logs. Plan on using the single
stepping/watch capabilities of simulators. Synopsys DVE works great for the test bench debugs. This step means extra time but trying to solve all debugging needs using logs would reduce the logging efficiency.

 

12. Put enough note verbosity message to be able to figure out the timestamp from where the dumps needs to be started and if you can decide if the dumps are needed that would be great.

 

Test Bench issue Preventions

 

0. Go defensive and be paranoid in terms of coding. Next time you are 100 % sure to find the element you are going to look for in the queue where you are tracking transaction completion still add an fatal error statement if its not found. These checks go a long way in catching the issue at root. Otherwise these can morph in to very tricky failures.

 

1. Having lots of failure with the similar error message but for a different causes is an indication of more granular checks are needed. More granular checks make it easier to debug.

 

2. Pay attention while doing copy/paste to avoid those extra compile cycles and painful debug cycles.

 

3. One aspect that is different coding in SV compared to C/C++ is the time dimension. Be aware that
hardware interfaces are parallel while something is being processed at one interface there can be activity on the other interfaces as well. This thought process can save you from normal items that come in as a part of dependency but also take care of race conditions.

 

4. Multiple threads accessing the shared resources is one more issue. While one writes the code it might be tough to imagine the concurrency of threads. Build your own way to imagine this concurrency and put the  needed protection of the semaphores.

 

5. Zero time execution is another trap. Beware the vmm_channel put and get are blocking. What it means
is on every channel put/get the scheduling coin gets tossed again. All the contesting threads get a  chance to compete and execute. While in your head you may be thinking of only the two components connected by channel to be active but its not true other components can also get a chance.

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This a guest post by Verification Sudha

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Demystifying Analog & Mixed-Signal ASICs

Application Specific Integrated Circuits, ASICs, typically conjure up the notion of massively complex logic chips containing tens or hundreds of thousands (even millions) of transistors configured to solve a customer’s unique set of problems. Unlike multi-function standard product ICs such as a micro-controller that can find its way into a wide variety of applications, ASICs are designed for one specific application and generally for one specific product or product family.

 

 

To better understand the role and applicability of ASICs, it is important to briefly review their historical origins.

 

The first Integrated Circuits from the early ‘60’s contained just a few transistors and performed simple digital logic functions such as  “and”, “or”, “nor”, etc.  These were called SSI devices, meaning Small-Scale Integration. As photolithography techniques improved, more and more transistors could be built on a single sliver of silicon. Soon, chip companies were developing Medium Scale “MSI” logic function like flip-flops, buffers, latches, etc (10-100 transistors).  Large Scale “LSI” (100-1,000 transistors) and eventually  VLSI (up to 100,000 transistors) ICs followed, providing lower system costs and higher levels of performance. Today of course, we have digital chips in excess of a billion transistors thanks to advanced sub-micron lithography and the low voltage, high speed processes upon which they are built.

 

The first digital ASICs were built using a standard cell library consisting of fixed-height, variable-width ‘tiles’ containing the digital logic functions discussed above. The ability to reuse these blocks over and over saved time and money when designing a custom logic IC.

 

Analog ICs were initially comprised of a pair of matched transistors and soon expanded to include rudimentary Op Amps, Voltage Regulators, Comparators, Timers and much more. Analog applications typically involve much higher voltages so these ICs needed their own unique set of manufacturing processes. More recently, market demands for smaller size, higher speeds and lower power consumption have forced a merging of analog and digital functionality on a single silicon chip. Cells consisting of the basic analog building blocks discussed above were created and added to the digital libraries. These Analog cells were restricted to the digital fab processes developed for predominately logic applications.

 

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Today, most ASIC companies offer some degree of analog functionality as a part of their services. In many cases, the analog functions are mimicked with digital design techniques. In others, compromises to the analog functionality must be made to facilitate the use of standard library cells that are designed to yield well in the fab processes developed for high speed, high density, low power digital designs. Often, these chips are referred to as Mixed-signal ASICs or as big “D”, little “A” ASICs, meaning high digital content and minimal analog content.

 

Analog ASICs play a critical role in our lives. Without them, none of the portable electronic devices we use in our daily lives would exist. Imagine a world without Cell Phones, MP3 players and Navigation Systems. Building them with standard products would make them prohibitively expensive and physically impossible to carry in our purses or pockets. Every automobile contains dozens of ASIC chips for everything from climate control to airbag deployment; suspension control to entertainment systems. ASICs also play important roles in applications for hospital medical equipment, eMeters, home appliances such as washers and dryers, scuba gear, hearing aids, and much more.

 

The Analog ASIC market is huge. In fact, research firm, IC Insights reports that almost 60% of the nearly $37B of Analog ICs sold in 2010 were ASICs. Yet very few mixed-signal ASIC design houses fully understand the implications of custom Analog design and its applicability to Analog centric ASICs. ASICs requiring high Analog content should be directed to those design houses that specialize in Analog circuit design rather than those who simply select Analog IP blocks from a library. Analog ASIC companies have large staffs of competent, well-experienced, Analog engineers with expertise in a wide range of Analog functions. The following table offers a range of these required design skills.

 

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Reviewing an ASIC house’s patent portfolio as a quick guide as to the creativity of its engineering team will serve as a first order measure of its Analog expertise.

 

Clearly, the large Analog IC houses (like ADI, Linear Tech, Maxim, National, TI) have patent portfolios a mile deep. Those that also engage in Analog ASIC development set high bars regarding who can access this capability and impose high minimum order requirements.  For example, TI reports that their application-specific analog business focuses on a small number of large customers like Seagate, Sony, Samsung, Hitachi Global Storage Technology, Toshiba and a few others that require custom application-specific products. Minimum annual unit and or dollar volumes force the majority of the smaller customers to seek out independent Analog or Mixed-signal ASIC design houses.

 

 

Myth #1. It is only economical to integrate Analog Functions into an ASIC if the Analog content is minimal.

 

The ASIC concept began as an integration tool to lower the costs of computationally heavy logic circuits. Today, after 30+ years, ASICs remain heavily digitally oriented.  When we hear the terms like SoC (System on Chip) and Re-useable IP (Intellectual Property) associated with ASICs, we often think of the massively complicated, digital centric ASICs that may contain a few important analog functions. Historically, it is these products that have garnered the attention of the media and established a mind set among the user community that a little Analog can go a long ways. But what about the applications requiring Analog centric ASICs? These are SoCs as well, even though they may not contain a uP core or even memory.

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The medical/industrial world is rife with such requirements yet most ASIC companies are quite unprepared for the challenges of hand-crafting the unique Analog circuitry required for these important applications.

 

 

The actual manufacturing cost of the ASIC chip may imply a huge savings when compared to the collective costs of the ICs it replaces. However, there are other costs associated with the ASIC that must be considered and amortized over the life of the product. Non-Recurring Engineering costs, based on the complexity of the design as well as hard tooling costs such as masks and test hardware, can add a few pennies or a few dollars to the ASIC chip cost, depending on the complexity and lifetime volume of the device.

 

Incorporating elements into the chip that require more exotic processes for features like high currents or low noise or high frequency will increase the cost of all the elements in that chip. Therefore, it is as important to know what to incorporate into the ASIC as it is to know what should remain a discrete component. Interestingly, the use of multiple smaller, less complicated Analog ASICs, differentiated by their manufacturing processes, can offer surprisingly stunning cost reduction results.

 

Most Analog applications use a collection of passive elements and discrete transistors in addition to the ICs involved. Integrating as many of these components as possible to the ASIC often comes for free and can have a dramatic effect in lowering the end product’s total assembly cost.  It is this potential total system cost saving that bolsters the justification to develop the Analog ASIC.

 

 

Myth #2. Mixed-Signal ASIC means the same thing as Analog ASIC

 

While the term “Mixed-Signal” implies a combination of Analog and Digital circuitry on a single chip, there is a distinct difference in the skill levels required to combine library cells (Analog and Digital) on a silicon chip versus actually creating an Analog design that uniquely satisfies all requirements of the specification. For many applications, Analog library cells offer sufficient performance to meet the system requirements.

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However, more and more frequently, the increased sophistication of the Analog application necessitates designs that are truly ‘application specific’ and not a compilation of general-purpose Analog cell blocks.

 

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Like the big Analog IC companies, true Analog ASIC companies employ experienced Analog designers who are artisans at Analog invention. Many of them have spent years at the big Analog companies, learning from the industry gurus.

 

Be careful not to let a Mixed-signal design house negotiate you away from your ideal specification. Close isn’t good enough…analog must be exact.

 

 

Myth #3. Only Ultra-high volume applications can benefit from Analog ASICs.

 

As noted earlier, many large semiconductor companies focus their ASIC efforts onto a handful of very large customers. Clearly, these are the privileged few and everyone else must seek out development and manufacturing partners that can and will match their needs.  All full service ASIC houses have their own business criteria regarding minimum NRE, tooling and most importantly, annual volume.  Some ASIC houses avoid the issue by just offering design services and leaving the issue of manufacturing to the customer. Either way, it is often the subcontract wafer fabs rather than the ASIC companies themselves that dictate minimum annual volume restrictions.

 

The semiconductor industry operates in alternating cycles of boom and bust. A brief look back in time reveals that in boom times, capacity at the big Asian foundries fills quickly and all but the most promising, high volume customers are turned away. Aggregators have somewhat mitigated the problem by combining numerous smaller company requirements under the umbrella of their larger purchasing power. However, the large Asian fabs are built to benefit from economies of scale, offering processes tailored for the mass market; high density, lower power logic. For many, Analog is problematic. Fortunately, there are bountiful alternatives.

 

Throughout the world and in particular in Silicon Valley, there are numerous ‘boutique’ wafer fabs that specialize in Analog processes and are not loathe to accepting lower volume business. Considered a well guarded secret by many, these fabs welcome low and moderate volume Analog business and offer pricing quite competitive with the billion dollar fabs in ASIA. These smaller fabs have come to realize that while Analog designs are often focused on lower annual volumes, Analog in general has shown to be less susceptible to the violent supply/demand curve swings inherent to the general semiconductor industry.  An additional attribute is that often Analog chips can sometimes remain in production for as long as ten years or more. For the fabs, accepting reduced annual volumes becomes an annuity that offers payback for years to come. Experienced Analog ASIC companies have spent decades nurturing these relationships for their customers.

 

Myth #4. Using existing IP from Analog Cell Libraries lowers the chip cost.

 

Using predesigned, functional cells such as amplifiers, converters and transceivers can shorten development time and therefore has a ripple through effect of lowering the chip’s total cost. However, even though design time is reduced, there can be other tradeoffs that must be considered.  Standard Analog library cells do not pack as neatly as digital cells. Using Analog library cells can result in blocks of unused silicon on the die that will needlessly lower the numbers of potential die on a wafer.

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Additionally, since the analog circuitry of a Mixed-signal ASIC is likely to be the input or output of the circuit, or both, these cells must be oriented closer to the periphery of the chip to facilitate easy access to bonding pads.

 

Handcrafting some or all of the Analog functions allows the designer to accomplish several things.  In a Mixed-signal design, handcrafted Analog circuits are laid out to fill voids created when using standard digital cells, better optimizing overall silicon area utilization.

 

 

 

 

Moreover, handcrafting the Analog portion allows the designer to determine precisely the performance parameters of the circuit rather than be restricted to the fixed performances of a limited number of standard cells available in the library.

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The conundrum of using overdesigned cells is another consideration worthy of the designer’s attention. As an example, for a given application, some analog parameters may be able to be relaxed, simplifying the handcrafted design compared to a standard cell. Alternatively, handcrafting the Analog circuitry affords the designer an ability to improve other performance parameters that can have far reaching implications that make the ASIC less costly in terms of test yield and thus more competitive in the marketplace.

 

 

Myth #5.  Cell based ASIC designs ensure product differentiation

 

Designing the Analog portion of a Mixed-signal ASIC using a Cell Library is tantamount to designing a system using standard, off-the-shelf, Analog ICs…with one key exception…selection. At the board level, there are tens of thousands of IC Amplifiers, Voltage References, Converters and more from which to choose.  In a cell library, the designer is limited to choosing from to a few of dozen Amplifiers, Voltage References, Converters, etc. Performance compromises may be needed to accommodate these limited choices.

 

Analog centric ASIC development affords a perfect opportunity to rise above the competition. As noted earlier in this paper, nearly 60% of the worldwide Analog IC  market is ASICs. If you and your competitors are basing your designs around the same Mixed-signal Cell Libraries, both of you will have approximately the same performance specifications, dictated by the specifications of the library cells.

 

True product differentiation comes from invention. It is derived by creating uniqueness to a product not readily available to the competition. Cell Libraries fail to deliver the necessary uniqueness often needed in critical Analog applications.

 

Myth #6. Handcrafted Analog is too expensive, compared to standard cells.

 

There is a time and place where standard Analog Cells are more than adequate. Experienced Analog ASIC Design Houses recognize this and only offer full custom Analog Design when the need merits it.

 

Handcrafted Analog can create the differentiation required to break out of the pack with a superior performing chip and thus a superior end product for your customer.  Additionally, stepping back from the Cell Library approach opens up options for manufacturing, since Cell Libraries are typically developed for one process at one fab.  Broader use libraries are available that specify a process, for example, 0.35um CMOS, but have relaxed specifications such that they can be instantiated in multiple fabs.

 

Handcrafted Analog creates an unlimited set of manufacturing options, especially through the use of boutique foundries.  Many of the boutique fabs differentiate themselves by the variety of services they offer and their willingness to make adjustments to their processes to accommodate optimization of the chip’s performance.  A recent example is a circuit JVD developed for a major automotive component supplier. The chip required a high voltage MOSFET that was not available in the boutique foundry’s standard process.  Integration was critical to the success of the project, so the foundry and JVD worked together to create the needed device structure.  The subsequent design provided the high voltage robustness needed for the application while minimizing parts count and the physical size of the end product.

 

Non recurring engineering (NRE) costs are a compilation of several variables. These costs must be amortized over the number of chips produced during the lifetime of the product to determine their effect on the unit cost of the ASIC. When executed properly,  NRE costs associated with handcrafting the Analog circuitry return a disproportionately lower unit cost of the final chip. The key to success is Analog Design experience resident at ASIC House doing the integration.

 

 

Myth #7. The most cost effective solution is to pack as much as possible into the Mixed-signal ASIC chip.

 

In a recent posting on Linked-In’s Global Semiconductor Alliance GSA Networking Group Discussion page, an IP Market Analyst commented on the difficulty of integrating customer specific Analog into a predominately digital design, citing the need to have 3 or 4 preproduction runs. The product, an SoC for a PalPlus TV system, missed its release date by more that 1 year.

 

This case shows the problem clearly. Insufficient Analog expertise can get a Mixed-signal ASIC house and their customers into a real bind. Missing a product launch window by a year or more is the kiss of death. When the Analog component of the design is critical (for example, more than a basic A/D or DAC) it’s best to seek out Analog ASIC experts to perform the integration.

 

Moreover, splitting the functions into multiple chips should be considered when both the Analog and Digital content is excessive. The fact remains, Analog circuits perform better in non-digital fab processes. When possible (from a cost/yield/board space perspective) the long-term cost benefits of a dedicated Analog ASIC chip can be overwhelming.

 

 

Conclusions

 

The application will always determine the appropriate combinations of technologies that are best suited for the ASIC design. As our dependence on cognitive prosthesis devices (smart phones, Wii controllers, tablet PCs, IoT, etc.) increases, copper tethers disappear and Analog increases its dominance in ASIC designs.  MEMS advances have placed Star Trek style sensors in our daily lives. Medical imaging, sensing and monitoring continues to improve our daily lives. All of these and more increasingly rely upon better, faster, denser Analog circuit content.

 

When considering a new ASIC design, carefully consider the role Analog will play in its deployment. To minimize risk, choose your ASIC development partner carefully. Most of the time, Mixed-signal ASIC design skills will be sufficient. To minimize risk, seek out an Analog ASIC partner with the right Analog design skills and experience to match the application.

 

 

 

 

 

 

 

 

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This is a guest post by Bob Frostholm, Director of Sales and Marketing at Analog ASIC company, JVD Inc. (San Jose, CA.) www.jvdinc.com