Monthly Archives: June 2015

globalfoundries IBM

IBM, GlobalFoundries Deal to To Close July 1st

The tech world was buzzing during last October when IBM agreed to pay GlobalFoundries $1.5 billion to take over their semiconductor manufacturing facilities in East Fishkill and Vermont. The deal is now expected to close as of July 1st.

 

The closing of the deal will put to end months and months of regulatory approvals. It will also move thousands of employees from the IBM payroll over to the GlobalFoundries payroll. The plants will have new employees in East Fishkill, Dutchess County, and Essex Junction, new Burlington Vermont. This comes to many in the tech world as no surprise as GlobalFondries announced last year that they were looking to invest $10 billion over the next year in their facilitates, primarily in the facilitates in New York. The chip plant in Malta Saratoga County has a total of 3,000 employees another 3,000 construction workers. They plan on adding 600 staff employees to this plant by years end.

 

globalfoundries IBM

 

There’s been no immediate comment from IBM or GlobalFoundaries themselves about the closing, but the sources close to both companies are saying that the deal is definitely going to close. Both companies did admit in the past to the deal closing sometime at the end of 2015.

 

Local and state leaders along with the companies are saying that they feel the sale is a great way to preserve jobs and expand the company in the New York area. The deal interestingly comes at the same time as IBM being rumored to make yet another round of job cuts across the country. IBM has so far preserves most of their jobs in New York because of the contractual obligations between the state and the company. Other plants, have not been so lucky. In January, GlobalFoundries confirmed that they have offered jobs to all of the IBM workers that are part of the final sales but we don’t know how many offers have been given out so far.

fib

Focused Ion Beam (FIB)

Integrated circuit (IC) designers are learning that a technique long used on older process nodes is providing even more valuable benefits as they develop devices to be manufactured at advanced technology nodes, including 28nm and beyond. During a period when it takes $10 million or more to bring a device to market, focused ion beam (FIB) circuit edit has become strategically important tool for reducing costs, optimizing performance and functionality, mitigating risk, and speeding time to market for complex device designs.

 

It is widely understood that IC designers will encounter many new problems at advanced process nodes that would be difficult, if not impossible, to anticipate based on previous design work. EDA tool providers are already addressing the difficulty of advanced node design with advice around design flow and other ways to handle numerous technical challenges. In addition to applying these new design flow modifications, developers can also apply FIB circuit editing to the process of debugging and validating fixes or exploring design optimization changes, before committing to the high cost or lengthy timetables of a full mask spin.

 

Tackling Challenges at Advanced Process Nodes

Design success barriers are magnified at advanced process nodes, where mask costs are high and it is more difficult to find and fix bugs. It is widely understood that designers will encounter many new problems at advanced process nodes that would be difficult, if not impossible, to anticipate based on previous design work. The feature sizes of chips manufactured at 20nm process nodes are 10 times smaller than the wavelength of the laser light typically used in lithography. Pre-silicon testing is growing extremely tedious, simulation times are growing excessive, and many designs simply cannot be 100 percent verified. Simulation models may be imperfect for extremely complex designs, and packaging can cause stresses to sensitive devices.

 

Challenges in this environment range from multiple patterning and layout dependent effects (LDE) to the use of local interconnect layers. Design and integration complexity rises to a new level with each new technology node. Server signals and power electro-migration also create challenges. Decreasing metal pitch leads to coupling effects and signal integrity issues. Increasing wire and via resistance requires more advanced and variable wire sizing and tapering techniques. Additionally, extraction, timing, signal integrity analysis, and modeling pose a multitude of variation issues that designers must solve before they can achieve accuracy without compromising performance. Lithography limitations at 20nm often require a great deal of fixing to achieve signoff. Finally, designers face numerous chip and IP integration challenges, packaging issues, and additional complexity as these issues interact.

 

Similar challenges face designers of power control ICs and devices that combine control with power FET functionality. In these design environments, FIB circuit edit techniques similarly provide benefits at advanced process nodes, and will be increasingly important as many power devices move to silicon carbide (SiC), gallium nitride (GaN), and other wide badgap materials.

 

Many EDA tool providers are already addressing these issues with advice around design flow and other ways to handle numerous technical challenges. This isn’t sufficient, however. In addition to applying new design flow modifications, developers can also apply FIB circuit editing with their early prototypes during de-bug. The same techniques can also be used to explore design optimization opportunities, by quickly and inexpensively implementing and creating physical prototypes that can be tested and validated before committing to the high cost or lengthy timetables of a full mask spin. FIB-edited device prototypes can be used to guide one-time modifications to masks, eliminating the need for a trial-and-error approach with successive versions of masks.

 

Overview of FIB Circuit Edit Capabilities

FIB systems have a number of uses in the semiconductor industry, microelectromechanical system fabrication, and biological studies. A primary use of FIB systems in the semiconductor industry is for circuit edit, allowing designers to cut traces or add metal connections within a chip (see FIg. 1). FIB edits can be performed quickly and easily, at a small fraction of the $5 million to $10 million in costs that are typical for a new lot of wafers in a fab. Using today’s state-of-the-art equipment, it is possible to edit circuits fabricated with 28 nm and smaller technology nodes that feature multiple layer metal stacks and occupy flip chip and other advanced chip scale form factors.

 

Multiple connections and cuts are shown for front-side FIB circuit edit.

Fig. 1: Multiple connections and cuts are shown for front-side FIB circuit edit.

 

FIB circuit edit is performed using a finely focused gallium (Ga+) ion beam with nanoscale resolution. It is possible to image etch and deposit materials on an IC with an extremely high level of precision. By removing and depositing materials, FIB circuit edit enables designers to cut and connect circuitry within the live device, and to create probe points for electrical test. It is the equivalent of performing microsurgery on IC devices. The high-energy Ga+ beam can mill through conductors, and uses various types of gases to either enhance milling precision or more effectively deposit conductive and dielectric materials. For instance, by using appropriate gas chemistries, a choice of tungsten, platinum, or silicon dioxide can be very precisely deposited using the ion beam.

 

In order to perform circuit edits, the FIB tool is coupled to a CAD navigation system that makes it possible to locate the area of interest. FIB circuit edit typically uses the designer’s GDS files to navigate to the precise area. This provides a method to find subsurface features and ensuring that the right edits are made (see Fig. 2). Accurate beam positioning is one of the most critical requirements for FIB circuit edit.

 

CAD layouts are used to perform FIB circuit edits.

Fig 2. CAD layouts are used to perform FIB circuit edits.

FIB Circuit Edit Applications

There are many uses for FIB circuit edit at every commercially available node. It can be used both to verify design change on the tester, and to validate design change at the system board level. Typical applications include:

 

  • Debugging and optimizing devices that are already in production — FIB circuit edits are often performed once a design flaw has been identified. This ensures that the proposed fix will completely resolve the problem. Designers can repair mask errors and know that the device will work after one and not two mask spins, while simultaneously expediting the next steps by getting working prototypes into customers’ hands so they can continue software development. As cycle times in mobile device and other market segments become more and more compressed, avoiding a week of lost cycle time can be extremely important for a successful product roll-out.
  • Exploring and validating design changes — more than just simulation that is required to optimize designs. FIB circuit edit goes beyond to the ultimate in emulation capabilities. It enables designers to try derivatives of device designs and observe the results. They can explore options like cut-away fuses or other functional changes, and experiment with them on a live device before committing to the cost or timetable of a complex mask spin.
  • Prototyping new devices without costly and time-consuming mask set fabrication — FIB prototype devices are often used to enable next-level testing. This enables developers to get a jump start on the next round of device debug and accelerate design cycles. FIB circuit edit eliminates the need for multiple prototype testing rounds and mask modification cycles. Designers can implement and evaluate the results of circuit changes on physical prototypes that will optimize or correct flaws in the design before committing to them in a new mask spin. What would otherwise cost $5 million to $10 million in wafer costs and 6-8 weeks in wafer processing cycle time can be done for hundreds or thousands of dollars in a matter of hours, ensuring that only one additional wafer spin will be required.
  • Duplicating and scaling fixes: Once a fix has been verified on a prototype using FIB circuit edit, it is possible to duplicate that fix on handful or tens of devices to provide internal test, validation, and qualification teams and even customer samples. By doing this, further system or application development work can then take place in parallel while waiting for the mask spin and final production devices to come back.
  • Accelerating time to market: Delivering on time is vitally important to customers. Their product designs are essentially on hold until they can get devices. FIB circuit edit speeds up the entire cycle. It gets customers into production and avoids loss of repuation or the risk of competitors getting their foot in the door, etc. Some large OEM customers also impose late delivery penalties that can sometimes reach millions of dollars.

Fig. 3 shows the best approach for integrating FIB circuit edit into the overall IC development and testing process.

FIB circuit edit can be inserted both at the simulation stage and later during de-bug to optimize success rates during the IC design process.

Fig. 3: FIB circuit edit can be inserted both at the simulation stage and later during de-bug to optimize success rates during the IC design process.

 

In the power semiconductor arena, most current control products are fabricated using traditional silicon technology, and FIB circuit edit is performed in much the same way with these devices as it is with any other analog or digital circuit. In the future, there is a strong possibility that drivers will move to wide bandgap materials. FIB circuit edit should offer benefits for these devices, as well. SiC, GaN, and other wide bandgap semiconductor materials enable power semiconductor devices to withstand high voltages and temperatures, while providing higher frequency response, increased current density, and faster switching speeds. At the same time, however, they present complex challenges related to design and characterization, process monitoring, and reliability. Challenges become even more difficult at advanced process nodes.

 

 FIB Circuit Edit Techniques Continue to Improve

There is a relatively common misperception that FIB circuit edit only works well at 90nm and 65nm process nodes, and that it has “run out of gas” at anything below. This is simply not true. Thanks to tool and methodology advances that have been derived from the experience of dedicated teams running thousands of circuit edit hours/months, FIB circuit edit can now be used for more precise beam guidance, operate in smaller areas, perform more intricate operations on both the back and front sides of the device, and handle copper layers.

 

A major development area for FIB circuit edit is the ability for tools to provide better aspect ratio for smaller cuts as part of the solution. FIB systems continue to deliver greater benefits thanks to advances in areas such as ion beam resolution, operating software, and CAD navigation. Ion beam resolution advances, alone, have delivered significant new capabilities that have been critical for recognizing small features, aiding in visual end-pointing, enabling precise CAD alignment, and improving box placement accuracy. Fig. 4 shows resolution advances that have been achieved from 2008 to the present.

 

The image on the left shows bit lines on a 90nm process in 2008, while the image on the right shows the bit line for a sub-25nm device today. [photo courtesy of DCG Systems].

Fig. 4: The image on the left shows bit lines on a 90nm process in 2008, while the image on the right shows the bit line for a sub-25nm device today. [photo courtesy of DCG Systems].

 

Tool advances are only part of the story, however. Because FIB tools are not entirely automated, there is no under-estimating the critical importance of FIB operator experience to circuit edit success. For example, endpoint detection, or the ability to know when selected layers of interest have been successfully etched, continues to require a high level of skill in order to achieve high success rates. Operator skill in this area is even more important at smaller geometries, and during particularly challenging FIB operations. Also important is the unique operator knowledge in such areas as IC circuitry, IC process technology, ion milling patterns, and general FIB tool usage basics.

 

Achieving this expertise can be difficult for an in-house operation. Often, larger semiconductor companies who already conduct some level of circuit edit will augment these resources with external service labs that have deeper and more extensive experience in solving the toughest FIB circuit edit challenges. As for small- and mid-sized companies, few can bear the expense of purchasing a FIB tool that might cost $1 million or more. Even if they could afford the tool, it would be difficult to staff a team with the necessary experience to most effectively operate it. Most companies of this size tend to go directly to an external lab that can implement circuit edits to support basic electrical design characterization or verification of redesign parameter, and offers a full range of debug tools necessary for solving difficult logic failures and other anomalies.

 

Best Practices for FIB Circuit Edit

There are numerous prerequisites for FIB circuit edit successes, including:

  • Tools: High resolution is particularly important at advanced nodes such as 28nm and 20nm. Designs generally require a .1um resolution (or aspect) ratio as well as a trenching approach that supports a finer resolution in order to make these edits. The smallest hole that can be made with today’s equipment is 0.1×0.1um with an aspect ratio of 1/20. For most 20nm and 28nm designs, it is impossible to make a small enough hole to reach the target. As a result, specialized FIB techniques are required in order to lower the aspect ratio and gain access to the target. The system must be able to smoothly remove dummy metal above the target metal layer. This also requires deep and extensive knowledge of IC circuitry and processes, FIB tools, and ion milling patterns. Figure 5 shows a typical back-side trench.
    Today's trenching approaches support fine enough resolutions to enable FIB circuit edits at advanced nodes.
  • Fig. 5: Today’s trenching approaches support fine enough resolutions to enable circuit edits at advanced nodes.
  • Back-side and front-side editing: Many erroneously believe that flipchip FIB circuit edit can only be performed from the top of the device, and that neither back-side nor front-side editing are possible. On the contrary, back-side edit is frequently the most effective way to operate. This might be true because of substrate material in flipchip packaging, or because of the increased number of metal circuit layers in today’s ICs, which makes it harder to reach a lower layer when editing from the top. Fig. 6 shows a back-side FIB circuit edit in which a resistor is introduced across two nodes.
  • Back-side FIB circuit edit is used to introduce a resistor across two nodes.
  • Fig. 5: Back-side FIB circuit edit is used to introduce a resistor across two-nodes.In another example, Fig. 7 shows a typical back-side FIB circuit edit in which a probe pad is formed for micro probing.High-resolution trenching enables edits at advanced nodes. [Image courtesy of FIB International Inc.]Fig. 7: High-resolution trenching enables edits at advanced nodes. [Image courtesy of FIB International Inc.
  • Handling copper layers: Most 28nm and 20nm devices are copper devices that feature a crystal structure which is very difficult to remove smoothly. Special methods are required, as well as the engineer’s experience so that the metal can be removed smoothly with a very high level of quality. Also, accurate beam positioning is more challenging for copper metal devices due to the non-visibility of the circuit patterns. This is also important for aluminum metal devices if there are no unique patterns to recognize on the top level.
  • Companion failure analysis and test tools, expertise, and capabilities: Because most devices must ultimately find their way into packages, there should be a smooth transition to de-capping or de-lidding the devices and performing micro-probing and other de-bugging tests on FIB-edited parts.
  • Front-end expertise: In addition to presenting challenges due to ever-shrinking nano-scale geometrics, semiconductor advanced technology nodes also introduce new front-end materials as processes evolve. FIB circuit edit labs can benefit from being part of a larger lab environment characterized by a significant level of front-end process understanding and materials expertise. Labs that support process R&D activity and yield support will be able to offer an advantage and insights, as well as other know-how that will help maximize the success of FIB circuit edit strategies.

 

Growing in Value

IC design verification and validation will continue to increase in difficulty as the industry moves down the nano-scale geometry curve. While some may believe that FIB circuit edit is obsolete at today’s advanced nodes, it is actually becoming increasingly valuable for improving the success rates for these designs, which often can cost $10 million or more to bring to market. Due to advances in both tool technology and best practices, FIB circuit edit can be used at advanced nodes for a variety of purposes, including debugging and validating fixes, as well as earlier in the process to explore opportunities for design optimization without  having to commit to an expensive and time-consuming full mask spin.

 

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This is a guest post by EAG  that provides semiconductor and electronics design firms worldwide with test, debug, and early engineering support.

ESD

CDM ESD Testing: Getting a Clearer Picture

Of all of the component-level ESD tests available, the CDM ESD (charged-device model) test is the closest to simulating real world events. CDM ESD testing simulates ESD charging followed by a rapid discharge, similar to what is seen in the automated handling, manufacturing, and assembly of IC devices. Unfortunately, the CDM ESD test sometimes gives confusing results. Some examples include the following:

 

  • Different results are seen when a part is stressed at different labs, even at the same voltage level.
  • A part tested at +/-450V fails, but later passes at +/-500V.
  • A part tested at +/-250V passes, but another sample of parts from the same lot fails at +/-250V.

EAG has investigated some of the more common causes of variability in the CDM test. Incorrect measurement of the current-versus-time waveform, which occurs during the discharge event, has been found to be the most important source of variation. Better measurement of the CDM waveform, using higher-bandwidth oscilloscopes to eliminate system-to-system variation, leads to more repeatable test results. This will become even more important in the near future when the ESDA and JEDEC release their joint CDM specification.

 

Overview of the JEDEC CDM ESD test

 

Figure 1, from JESD22-C101F, shows a generic CDM test circuit. It includes a discharge head with a pogo pin, a 1Ω radial resistor, the top ground plane, a semi-rigid coaxial cable, and the test head support arm. The test head is robotically driven, and it often has two small cameras that are used to align the test head in the correct position over the device under test (DUT). The potential of the DUT is raised by the field-induced method. A test voltage is applied to the field-charging electrode. The DUT sits in the “dead bug” (pin up or ball up configuration) on an FR-4 dielectric that covers the field-charging electrode. Once the DUT has been charged, the device is discharged by having the pogo pin touch each DUT pin, one at a time. At least one positive and one negative discharge is applied to every DUT pin. If the DUT no longer meets its data sheet specifications after the CDM stress, it is considered to be a failing unit.

generic cdm circuit

Figure 1 – Generic CDM Circuit

 

The CDM tester is verified to be in spec by using a 1GHz/5Gigasamples/sec oscilloscope to measure the current-versus-time waveform when the DUT is one of the standard JEDEC capacitors. The specifications for the small and large disk capacitors are found in the JEDEC CDM specification, JESD22-C101F. The generic discharge waveform is shown in Figure 2.

 

cdm discharge waveform

Figure 2-CDM Discharge Waveform

To be in spec, the waveform must have characteristics that meet the requirements defined in Table 3 of the CDM specification.

Table 3-CDM Waveform Characteristics

 

Common Sources of CDM Test Variability Can be Controlled or Characterized

In the CDM test, it is relatively easy to raise the field-charging electrode to the proper voltage. Unfortunately, the correct voltage on the charge plate is insufficient to guarantee a repeatable CDM event. Most of the variability in the CDM test comes from the discharge event. The sources of variability include the following:

  • JEDEC test head differences
  • Waveform measurement
  • Charging time
  • Size of ground plane
  • Pogo pin variables (size, cleanliness, etc.)
  • Capacitor disk
  • 1Ω radial resistor
  • Humidity control (<60%)

Most of these sources of variation can be characterized or controlled. Although no two JEDEC test heads are alike, the test head differences can be electrically modeled. The charging time can be controlled by the CDM system software. The ground plane can be manufactured to tight tolerances. The correct type of pogo pin can be obtained, and the pogo pin can be cleaned before every test run. The capacitor disk can be cleaned before each use. The 1Ω radial resistor can be measured accurately with a four-point probe, and the software that analyzes the waveform can take the measurement into account when computing Ip. Flowing dry nitrogen in the CDM chamber provides humidity control and a more repeatable result. Even if these issues are resolved, however, there still is the challenge of system-to-system variation caused by differences in oscilloscope resolution.

 

The Bigger Variability Issue: Effects of Inadequate Temporal Resolution

EAG has shown that CDM waveform measurement using 1GHz/5Gs oscilloscopes is the largest source of system-to-system variation. This is consistent with findings by leading semiconductor manufacturers. The issue is temporal resolution, or the sampling rate of the oscilloscope. The analogous parameter for visual phenomena is spatial resolution, as shown in Figure 4.

increasing spatial resolution 1    increasing spatial resolution 2    increasing spatial resolution 3

Figure 4-Increasing the Spatial Resolution

The image is not clearly recognizable unless there is adequate spatial resolution. The same is true for the CDM waveform. The waveform cannot be measured correctly unless the oscilloscope has a high enough sampling frequency.

The current JEDEC specification specifies a 1GHz/ 5Gigasamples/sec oscilloscope to capture the CDM event. Digital oscilloscopes attempt to reconstruct waveforms using samples from an analog-to-digital converter and a sin(x)/x interpolation algorithm. The sampling rate imposes limitations on the ability of the instrument to render an accurate waveform. The Nyquist criteria state that a signal has to be sampled at least twice as fast as its highest frequency component in order to correctly reconstruct it. This is based on the following assumptions:

  • The waveform can be represented as a superposition of different frequency sine waves.
  • An infinite (or very large) number of samples is available.
  • The waveform repeats indefinitely.

Unfortunately, the CDM event does not fit these assumptions. First, the CDM waveform has higher frequency components, primarily due to extra components added to the JEDEC test head to shape the waveform. Next, the oscilloscope sampling rate does not allow for a large number of samples to be taken. Finally, the CDM event is a one-shot event; it does not repeat indefinitely.

When a 1GHz oscilloscope is used to measure the CDM current versus time waveform, the display looks like the first picture in Figure 5. Because the resulting waveform seems to be similar to the waveform shown in the CDM specification (see Figure 2), the waveform appears to be correct. If the interpolated data points are removed, however, and the actual samples are displayed, the waveform looks like the second display in Figure 5 — a considerably different picture. Two to three data points define the rise time. Three to four data points define the pulse width. The peak current will not always be captured correctly.

Current (A) vs Time (ns), 1 GHz oscilloscope, interpolated and actual data points  Current (A) vs Time (ns), 1 GHz oscilloscope, interpolated and actual data points

Figure 5-Current (A) vs Time (ns), 1 GHz oscilloscope, interpolated and actual data points

Although it is possible to model CDM test head characteristics and apply calculations to deconvolve the 1GHz CDM waveform, the better approach is to use a higher bandwidth oscilloscope.

 

A Better Approach

When the same CDM waveform shown in Figure 5 is measured with a higher-bandwidth, 8GHz, rather than 1 GHz, oscilloscope, the true shape of the waveform can be seen more clearly. This is shown in Figure 6. This waveform shows the higher frequency components of the CDM waveform. When the interpolated data points are removed, the resulting display retains the same characteristic shape. This is also shown in Figure 6.

Current (A) vs Time (ns), 8 GHz oscilloscope, interpolated and actual data points  Current (A) vs Time (ns), 8 GHz oscilloscope, interpolated and actual data points

Figure 6-Current (A) vs Time (ns), 8 GHz oscilloscope, interpolated and actual data points

A 1GHz oscilloscope with 5Gigasamples/sec does not have adequate resolution to make accurate measurements on the JEDEC CDM waveform. Because the waveform in the ESDA specification is faster and narrower, there is an even greater need for a higher bandwidth oscilloscope. This is likely to continue to be the case when the joint ESDA/JEDEC CDM specification is released.

 

EAG CDM Capabilities

To insure that the CDM waveform is measured correctly, EAG is taking the following actions to minimize variation:

  • Use an 8GHz oscilloscope in 5Gigasamples/sec mode to meet old JEDEC and ESDA specs.
  • Correlate 8GHz/40Gigasamples/sec s oscilloscope measurements to 1GHz/5Gigasamples/sec measurements for the existing JEDEC and ESDA specs. The result will be a revised version of the CDM waveform characteristics table that has the correct waveform parameters for measurements made with an 8GHz oscilloscope.
  • Offer the option to set up the existing JEDEC and ESDA tests using the aforementioned new table.
  • Offer the option to capture actual waveforms on client parts to help them understand and model the effects of the CDM event for their products.
  • When the new CDM specification is released, use an 8GHz/40Gigasamples/sec oscilloscope to verify and center waveforms, as allowed in new specification’s waveform table.
  • Encourage clients to move toward the new joint ESDA/JEDEC spec when it becomes available.

EAG has equipped its ESD labs with 8GHz oscilloscopes and latest testers to minimize CDM variation. EAG will be equipped and prepared to test to all CDM standards and will continue to lead by developing and bringing support for current standards and protocols to our customers.

References

JESD22-C101F, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

JEP157, Recommended ESD-CDM Target Levels

“CDM Tester Properties as Deduced from Waveforms”, Timothy J. Maloney and Nathan Jack, 2013 EOS/ESD Symposium

 

_______________________________________________________________________________________

This is a guest post by EAG that provides semiconductor and electronics design firms worldwide with test, debug, and early engineering support.

tsmc xlinix

Xilinx Expected to Introduce new 7nm Products in 2017

The war between TSMC and Samsung is heating up and it’s expected to last well throughout the decade. The war only got hotter when TSMC announced that they will begin producing 7nm processors in 2017. Xilinx will be their very first customer.

Xilinx Inc. made the announcement late yesterday that they’re going to collaborate with TSMC on the 7nm process and 3D IC technology for the very next generation of All Programmable FPGAs, MPSoCs, and 3D ICs. This technology is the fourth consecutive generation where two companies have joined forces on an advanced process and CoWoS 3D stacking technology.

 

tsmc xlinix

The official roll out of the 7nm products by Xilinx is due to take place in 2017. The speed with which this industry changes is very surprising. TSMC recently made the switch to a smaller process note and they also uncovered back in February that development of their in house product InFO-WLP technology was going to be the first to market with their foundry’s 16nm FinFet process manufacturing beginning in 2016. Then, it will be ready for more-advanced use in 10nm process beginning in 2017.

 

Apple’s next iPhone is due to arrive in September and it is based on 14nm. The iPhone released in 2016 will be based on the 10nm technology. Apple’s devices will finally be powered by 7nm processors starting in 2017.

 

The president and Co-CEO of TSMC, Mark Liu, said that the company is “pleased to work with Xilinx to enable its fourth generation of breakthrough products.” This could be just the advantage in technology TSMC needs to get the jump on Samsung for years to come. It’s even possible this processor might be able to deliver enough power to the highly advance 3D/VR headsets that are all the technological rage.

semiconductor wafer1

Semiconductor Wafer – Overview and Facts

Semiconductor wafer is absolutely invisible in our daily life but it exists in a form of an ASIC or an IC in each and every electronic device we use. Semiconductor wafer is a round piece of silicon which consists of silicon dies that are designed to perform a very specific functionally. One can easily remember from school that silicon has an atomic number of 14 on the periodic table and has an atomic weight of slightly more than 28. But there are many other interesting facts you should know about semiconductor wafer.

 

Here are 10 important facts you need to know about semiconductor wafers:

 

1. Semiconductor wafers are made of silicon which is the second-most common element on the Earth (just after oxygen) and it’s the seventh-most common element in the entire universe.

semiconductor wafer1

2. As the sand used to produce the semiconductor wafers has to be a very clean, most of the sand used for these processes is shipped from the beaches of Australia. Not just any sand scraped off the beach can be used for semiconductor wafer production.

 

3. Semiconductor wafers are available in a variety of diameters. In 1960 the first semiconductor wafer was manufactured in the US, the semiconductor wafer’s diameters was 1 inch. Today the standard semiconductor wafer size is 12 inch with foreseeable plan to achieve 18 inch semiconductor wafers.

 

4. Wafers are formed with a highly pure, almost defect-free single crystal material. The process to forming these conductors is called Czochralski. During this process, silicon or germanium is made by pulling a seed crystal from a melt. Baron or phosphorus can be added to the molten intrinsic material in direct amounts in order to dope the crystal. After doping the crystal the material is then turned in to a n-type and p-type extrinsic semiconductor.

 

semiconductor wafer2

5. Semiconductor wafers thickness will vary greatly. Wafer thickness is always determined by the mechanical strength of whatever material is used to make it. No matter what the semiconductor is made out of, the wafer has to be thick enough to support its own weight so it doesn’t crack during the handling process.

 

6. The use of extrinsic (pure) semiconductor wafer can be seen in many everyday electrical devices. An extrinsic semiconductor is a semiconductor that has been doped and is transformed in to a pure semiconductor. Applications such as Laser, Solar Cells are based on extrinsic semiconductor.

 

7. Even though silicon is considered to be the most prevalent material for wafers that are used in electronics, other compounds can be used as well. III-V or II-VI materials have also been used. Gallium arsenide or (GaAs) is a IIIV semiconductor that is produced during the Czochralski process. It’s often used as a common wafer material.

 

8. Die per wafer calculation is the first step for every engineer that wishes to find out the price of each die on a semiconductor wafer. Gross number of dies per wafer can easily and quickly calculated using AnySilicon free tool here.

 

9. In some specific applications the die per wafer is equal to 1 (one) which means that there is a single die on each semiconductor wafer. As the maskset reticle cannot cover the entire semiconductor wafer, a special stitching needs to be performed to connect the different tiles together. Some silicon wafer suppliers have very good experience in these types of applications.

 

10. Proper storage conditions are necessary to prevent contamination and/or degradation after shipment. Semiconductor Wafers that are not vacuum sealed must be placed in a Nitrogen (N2) cabinet with a flow rate of 2 to 6 SCFH (Standard Cubic Feet per Hour).

 

wafer

GLOBALFOUNDRIES Release Schedule for 14nm

The 14nm technology development between Samsung and GlobalFoundries that started last year is now reaching its final step by releasing the availability schedule of the process technology including the 2 main flavors.

 

 

The primary concept of the strategic collaboration is to make 14nm FinFET technology available at both Samsung and GlobalFoundries, giving customers the assurance of supply that can only come from true design compatibility at multiple sources across the globe.

Although the ramp to production was planned to start in 2014, GlobalFoundries only now releases the official schedule to the market.

 

Some major players might have already access to the technology to help GlobalFoundries run a few pipe cleaners and to ensure first paying customers. One of them, might be Apple.

 

 

The big hope for GlobalFoundries management is to win some of Apple’s production by running A9 project on 14nm technology node in GlobalFoundries Malta fab. According to a report by Bloomberg, Apple picked Samsung and GlobalFoundries over the world’s largest chip manufacturer, Taiwan Semiconductor Manufacturing Corp. But this seems not to be final decision of Apple.

 

GF14 nm