Monthly Archives: August 2015

SoC Manufacturing and Test Trends

Technology Trends


Process technology is progressing at a very fast pace and 16/14nm FinFET- based SOCs are available from various fabless companies. Significant investments in the development of advanced technology nodes are being made to ensure that future demands are met. This makes fab utilization of primary importance. To that end, SOC companies are accelerating the introduction of highly integrated products in these process technologies.


Custom SOCs designed for consumer applications and powered mostly by battery, must possess low active and stand-by power characteristics. FinFet (16/14nm) devices provide significant reduction in static leakage leading to lower power and high drive currents which in turn enable faster switching at lower supply voltages. Application of these process technologies is ideal for this application space.


For the first time, there is a fundamental change to the structure of the transistor (3D) resulting in new defect mechanisms creating a major challenge on the SOC design and manufacturing. In particular, FinFET critical dimensions are, for the first time, significantly smaller than the underlying node dimensions, leading to an increase in the number and complexity of layout and circuit-sensitive defects. This also means greater variability from design to design, making yield an ongoing challenge even as the process matures. New test structures and technology bring-up methodologies are necessary to control process induced variations while layout and circuit design needs to be optimized to mitigate this process impact.




It is important that both foundries and SOC design teams work together to better understand defects that could affect product quality and yield. There is a critical feedback loop that comes from yield information physical defect analysis. This data drives updates to DFM rules. Foundries have also identified that FinFET based memories have many new defect types, each categorized as a unique fault model. It’s critical to develop an optimized suite of test algorithms that detect these defects while keeping test cost low.


Jointly (fab and fabless design customer) driven DFX methodologies are being used to accelerate technology bring up and are now enabling customers fast volume ramp up.


DFT – Testability and Yield Improvement

At a high level, increasing SOC sizes including processors (>100Mgates), memories (100-200Mb), system interfaces, mixed signal blocks, various IPs and complex packaging have made SOC tests a tough challenge.


Designers have to consider various manufacturing related issues including DFT: How the IPs and other design blocks will be controllable and observable at top level; design for debug; yield ramp; and how the entire SOC can be tested without increasing test time and overall test cost.


In addition to reducing test cost, companies must focus on yield improvement, improve product quality and lower DPPM, in order to address the need to keep track of data for all phases of manufacturing.


In addition to DFT, DFM, DFY (Design for Yield), designers should consider the following issues:


  • Concurrent test of IPs, its impact on power dissipation
  • Device performance & power tuning like DVFS during test
  • Increasing test vector generation – for manufacturing test, characterization test, acceptance/quality test
  • Increasing size of test vectors – impact on test time
  • Maintaining Die/ package traceability
  • Data collection and data analysis, defect identification and yield improvement

Trends in Testability features


Advanced DFT methodologies are used to design and test special structures to enable fast failure analysis identifying design and manufacturing defects.


System and RTL design must include DFT features to meet design requirements such as: Impact of DFT on PPA (test power, test performance and test area overhead); testability coverage goals including stuck-at faults, transition faults and at-speed defects; automatic test pattern generation (ATPG) vectors; and test time.


Most SOCs use multi-power islands, DFT design has to be power domain-aware and construct scan chains appropriately leveraging industry standard power specifications like (UPF/CPF).


DFT IP like JTAG boundary scan, memory BIST collars, logic BIST (LBIST) and compression macros are readily integrated into the design and verified during the logic design process. BIST adoption is evolving beyond embedded memories to logic and mixed-signal blocks. In addition, adding test structures on chip enables greater test efficiency through increased test parallelization.


SOC designs must provide the capability to enable on-die circuitry (BIST, Logic DFT, etc.) and include design and test special structures to enable fast failure analysis identifying design and manufacturing defects. In the past, it was sufficient to identify failing bit and logic gate for yield improvement; however, in today’s environment we need to be able to isolate faulty blocks and replace with spares and even tune the performance.


DFT provides additional value for expensive on-chip test functions by using an external tester. By combining DFT solutions for an on- chip and off-chip tester strategy, we can improve speed test coverage. If designed properly, testing at speed or at multiple speeds, can be performed without the need for an external add- on hardware on tester. It also reduces the time-to-market window, while ensuring superior quality SoC designs and reduced testing costs.


Testability features continue to evolve to address the increased complexity of SoC and 14/16 nm FinFet process technologies requiring new fault models and identification of leaky power switches. With new technologies, whether in the form of new circuit design, a new algorithm or new IP modules, the EDA tools are being updated.



This is a guest post by Hem Hingarh, VP Engineering of Synapse Design

The IP licensing business model. A love story.

Some months ago my colleague Rys Sommefeldt wrote an article offering his (deeply) technical perspective on how a chip gets made, from R&D to manufacturing. While his bildungsroman production covers a lot of the engineering details behind silicon production, it is light on the business side of things; and that is a good thing because it gives me opportunity to steal some of his spotlight!


This article will give you a breakdown of the IP licensing model, describing the major players and the relationships between them. It is not designed to be a complete guide by any means and some parts might already sound familiar, but I hope it is a comprehensive overview that can be used by anyone who is new to product manufacturing in general.


The diagram below offers an analysis of the main categories of companies involved in the semiconductor food chain. Although I’m going to attempt to paint a broad picture, I will mainly offer examples based on the ecosystem formed around Imagination (since that is what I know best).



Enabling innovation in SoC IP_v3f
A simplified view of the manufacturing chain


Let’s work our way from left to right.


IP vendors


Traditionally, these are the companies that design and sell silicon IP. ARM and Imagination Technologies are perhaps the most renowned for their sub-brands: Cortex CPU + Mali GPU and MIPS CPU + PowerVR GPU, respectively.


Given the rapid evolution of the semiconductor market, such companies continue to evolve their business models beyond point solutions to become one-stop shops that offer more than for a wide variety of IP cores and platforms, comprising CPUs, graphics, video, connectivity, cloud software and more.


For example, Imagination has recently announced an entire range of reference IP platforms designed to accommodate the rapidly shifting IoT market. Take the smart sensor IP platform below: not only does it include the full hardware IP required to build a chip (a MIPS Warrior MCU andan Ensigma Whisper RPU), but it also comes pre-bundled with all the additional software required to connect the device to the cloud (the FlowCloud IoT API). Moving up the performance ladder, we find the connected audio IP platform, built around Caskeid – an innovative combination of hardware and software IP that delivers pitch-perfect wireless audio streaming.



Imagination, TSMC IP platforms - SoC IP-0IP platforms using MIPS, PowerVR and Ensigma


Revenue model

For any new deal signed, the IP vendor will charge an up-front premium called a license fee.


Based on factors such as the complexity of the IP, cost of development, target applications and expected volumes, a license fee can vary from 100,000s to 1,000,000s of dollars.


Once products using the IP start shipping, the vendor will also receive royalties. They represent a fraction of the total chip cost and can be between a few cents to tens of cents, depending on a range of factors, including the ASP (Average Selling Price) of a processor.


The royalty rate also varies over time as companies move to larger volumes.


IP licensing - revenue vs investment

Revenue vs. investment curves for IP


The diagram above shows you the ideal relationship between investment and revenue for IP; notice how companies must make a significant financial investment if they want to see a jump in revenue once that piece of IP reaches maturity.


The revenue curve assumes that mature IP eventually ships in extremely high volume, generating a significant return on the initial investment.



In terms of deliverables, there are generally two types of licensable hardware IP:


  • Off-the-shelf processor IP: fully designed and pre-verified RTL code (e.g. a PowerVR G6230 GPU) configured according to a customer’s specifications. This sounds like a trivial process but actually can turn out to be a very complex task; for example, you can read this article that describes how Imagination helps customers pick a PowerVR GPU for a 4K DTV and a smartwatch.
  • Architectural license: the semiconductor vendor receives the rights to design their own hardware implementation based on a set of specifications. Typically, an architectural license is granted when a silicon company with a significant internal design capability wants to radically differentiate from the competition or when it wants to target a specific market that is not served by existing, pre-designed off-the-shelf processor IP (or sometimes both). Some IP companies simply hand over the handbook and an architectural validation suite for a hefty fee and wash their hands clean; others take a different approach, working with the architectural licensee to offer a skeleton on which the SoC designer can build on (if needed).

Read When SoC met IP to learn more about the implications of licensing off-the-shelf IP and/or an entire hardware architecture.


Any license has complex legal implications but generally an SoC company looking to purchase IP will be presented with three options:


  • Single use: the silicon vendor is licensing one IP block (e.g. a MIPS P5600 CPU) for use in one chip
  • Multiple use: the silicon vendor is licensing one IP block (e.g. a PowerVR G6200 GPU) for use in multiple chips (e.g. a mobile SoC and a TV chip)
  • Subscription: the silicon vendor has unlimited access to an entire family/generation of IP (e.g. PowerVR Series6) and can use it in multiple chips

In addition, many IP vendors develop in-house physical IP to help SoC designers hit specific targets. Take the Design Optimization Kits (DOKs)for entry-level PowerVR Rogue GPUs for example: it is essentially a pre-verified package guaranteed to fit in a certain silicon area – a vital requirement for that specific market; there are also DOKs optimized to hit the high performance efficiency goals of the premium market.




Imagination + Synopsys DOK


DOKs are usually created for two processors in a family: the most popular (e.g. PowerVR G6200) and the smallest (e.g. PowerVR G6100).


The combination of the two guarantees you will likely hit the maximum number of customers interested in licensing from any given generation of IP.


Fabless semiconductor vendors


Fabless semiconductor companies like Actions Semiconductor, Allwinner Technology, AMD, Broadcom, Marvell, MediaTek, Microchip, Qualcomm, Rambus, Rockchip, Realtek, Xilinx – and the list goes on – are designers of the semiconductors that power many of our electronic products.


There are two main routes for fabless chip makers to design (parts of) an SoC: license from an IP vendor or produce your own in-house design. According to a recent chart presented at the 2015 Imagination Summit in Santa Clara, designing in-house processors takes 3-4 years and costs between 100-200 million dollars, on average. Meanwhile, licensing IP cuts the cost to $10-$50 million and reduces design time in half.


Another remarkable phenomenon is the degree of consolidation occurring in the semiconductor space; in the last three years alone, there have been some huge mergers and acquisitions – NXP/FreescaleAvago/Broadcom, and Intel/Altera being the most recent examples.



Ingenic JZ4780 (dual-core MIPS CPU, PowerVR SGX GPU)


One aspect that usually goes unnoticed is the amount of effort that goes into marketing a chip. Gone are the days when all you had to do is take a design into mass production and then simply count on the OEM to do the rest of the heavy lifting for you; now semiconductor vendors have to produce full reference platforms (notice a trend here?). Some even become a full-fledged OEM and start selling directly to consumers.


This occurs especially in regions like Asia where OEMs rely heavily on chip makers to ‘hunker down and git’er done’ – and sometimes that even means building a fully-certified, ready to ship device. Through collaboration with OEM/ODMs some semiconductor manufacturers are changing their value proposition and helping to deliver more complete devices to consumers.


Intel smartphone reference design


Finally, the consumer gets a device that costs considerably less than a similarly-specced flagship product.


EDA and pure-play foundries


Some prefer to keep EDA companies and pure-play foundries in separate categories but I like to lump them together based on the synergies that exist between them. The major EDA companies include Cadence, Mentor Graphics and Synopsys while pure-play foundries are represented by the likes of TSMC, UMC, SMIC and Globalfoundries.


Imagination maintains a very close working relationship with all of the above. EDA companies help us produce DOKs and also collaborate on designing test chips or FPGA prototyping rigs. These products help us better verify our designs before they enter production while EDA guys can also help their customers (semiconductor vendors) hit targets faster.



Synopsys routing tools at work


Here’s a little known fact: Synopsys and Cadence are also large suppliers of IP (some of the largest in the world by revenue and sheer breadth of offerings). Synopsys ships a wide range of CPUs and peripheral IP. USB, PCIe, DDR, SATA, HDMI, MIPI, Ethernet – you name it, they most certainly have it. Cadence on the other hand has recently acquired Tensilica, a strong contender in the DSP IP market.


Foundries like to keep IP vendors close because they can optimize process nodes and libraries on a broad selection of processors and architectures. This ensures they can service a larger customer base and adapt to ever-changing market conditions.


Turning sand into SoCs


Two relevant examples are the recent process nodes from TSMC designed for ultra-low power IoT devices – 16nm FinFET C (16FFC) and 28nm HPC+; they were introduced specifically to serve a growing desire to reduce power consumption for constrained devices such as wearables and IoT sensors.


OEMs and ODMs

Although many will look away thinking there isn’t a lot to see here, I really find this segment fascinating. I won’t focus too much on the history of device manufacturing or the leading companies today.


Instead, I will provide a quick snapshot of the rising stars in the East. If you think of the number of companies that really started from nothing five years ago (Xiaomi, OnePlus, OPPO, Meizu or Micromax, etc.), it is truly remarkable how quickly they have grown. Many enjoy cult-like status in Asia and seem to be getting exceptionally good at delivering true flagship products at very attractive prices.

The enormous success of these local heroes has been based on incisive marketing strategies and speaking directly to consumers: viral marketing campaigns that produce real resultsaffordable and usable devices that look goodaccess to local services, and customer support channels specifically tuned for regional requirements.


This back to the roots approach to product design and marketing gave Xiaomi, Meizu and others a big boost in popularity; soon, market share growth followed suit. In a big way.


Another interesting development is the increasing interest displayed by online service providers (particularly e-commerce companies) in becoming OEMs. For them, the hardware platform becomes less of a revenue stream and more of a strategic tool for delivering value-added services. The classic example is Amazon and the Kindle Fire program but Microsoft is another company worth following; a lot has also been written about the Alibaba Group recently acquiring a large chunk of Meizu.


Asus Zenfone 2 packs high-end features at a very affordable price


Finally, ODMs are striking some surprising deals too, moving beyond their traditional contract manufacturing role. When Nokia launched the Intel-powered N1 tablet (its first mobile device after selling off the Lumia brand to Microsoft), Foxconn emerged as a strategic partner, going into uncharted territory by handling distribution, sales and customer care, and reportedly even taking responsibility for liabilities and warranty costs.

The vertically integrated

Taking the vertically integrated route can offer substantial advantages if done right. Companies that are vertically integrated have a very tight grip on many aspects of manufacturing; there is a lot to be gained from the synergies that result.



Samsung offers optimized foundry solutions


I can serve up many examples of vertical integration in the semiconductor market; for the sake of time, I will focus on the three that I think are relevant today:


  • The semiconductor designer/foundry hybrid: the most well-known example here is perhaps Intel, known for their Atom, Core and Xeon microprocessors; another example is STMicroelectronics, a French-Italian IC design and manufacturing house strongly in favour of FD-SOI technologies.
  • The semiconductor designer/OEM hybrid: Apple holds the crown here in terms of popularity although there are many companies that have developed an SoC design arm. Examples include Amazon (Lab126), Huawei (HiSilicon), Panasonic (Panasonic SLSI) and LG (LG SIC).
  • The all-in-one hybrid: there is only one company that has brought together almost all aspects of manufacturing under one roof and that company is Samsung. Although the Korean juggernaut still relies on IP vendors for the building blocks of its processors, it has produced amazing large array of chips manufactured on leading edge process nodes; a recent teardown of a Galaxy S6 smartphonerevealed a vast majority of components that came out from Samsung’s own foundry and LSI group.

It will be interesting to see whether Samsung will remain the only semiconductor-foundry-OEM juggernaut or if anyone else will make a move.

Software developers

Obviously, I have kept the best for last (note: praise from hardware engineers is like catnip for software developers). This category is an important piece of the puzzle because it makes or breaks an ecosystem. You can have the world’s best hardware – if there is no optimized software to run on it, it will die a certain death.


Growing and maintaining an ecosystem requires considerable effort from hardware vendors. For example, many sources have confirmed that Intel employs more software than hardware engineers.

At Imagination, there are multiple teams writing software for MIPS CPUs; emulators, compilers, OS bring-up, customer support and many other tasks requiring a sizeable team of software experts.


The end(?)

There you have it! You’ve read about how semiconductors go from concept to product and now you’ve learned how different pieces of the business puzzle sit together.


No matter how the market evolves and irrespective of who survives, one thing to remember is the remarkable contribution made by all the companies mentioned here – and others too – to today’s rapid technological progress.



This is a guest post by Alexandru Voica which is a Senior Technology Marketing Specialist at Imagination Technologies

Comparing Au, Pt, Ag and Cu Wire Bonding

With the creeping rise in the price of gold, many microelectronics manufacturing companies have been looking for alternatives to reduce the cost of ball bonding. Recently, the trend has been to look into the use copper wire. However, there are many drawbacks to using copper wire, including the short shelf life of pure copper wire, EFO must occur in a forming gas (N2 + 3H2) adding cost and infrastructure, and Palladium-coated copper wire also adds cost to the wire.


In addition, because copper is harder than gold, bond pad structures must be scrutinized so the bonding does not damage the die. Pure silver wire has been tried as another alternative to gold but is often eliminated as an option due to the phenomenon of silver migration.


Silver (Ag) Alloyed Wire


IMAPS held their annual “Topical Workshop & Tabletop Exhibition on Wire Bonding” in San Jose, CA last month where a presentation was delivered on Silver (Ag) alloyed wire as an alternative to copper or gold wire. Within the last few years, some wire manufacturers have created silver alloy bonding wire with their own specific recipes for the alloy. Alloying silver has been useful to eliminate the silver migration phenomenon. The price of silver alloy wire is somewhere between Pd-coated copper and gold. Silver alloy wire has similar wire bonding properties, such as a similar hardness to gold. A couple of purported useful applications are in LED manufacturing and solar panels.


On the other hand, there are challenges in using silver alloy wire as well. With the alloys comes added electrical resistance, which is a negative for many applications. Also, silver alloy ball formation cannot be done in room atmosphere (it needs N2 only). There is also the drawback concerning the suitability of silver alloy wire to any given application; for example, it is probably not suitable for use in radio-frequency applications.


Platinum (Pt) Wire


In recent years, the price of gold has approached the price of platinum, making Pt a contending option for wire bonding versus Au wire. The excellent biocompatibility of platinum, combined with its good stimulation and sensing properties, makes this precious metal a top choice for use in life-saving cardiovascular implants such as defibrillators and pacemaker electrodes.




This is a guest post by Palomar Technologies, formerly Hughes Aircraft, which is the global leader of die attach solutions, wire bonding equipment, optoelectronic packaging systems and precision assembly services.



2.5/3.0D packaging: Path Finding



“We’re only qualified to 40 degrees …‘what business does anyone even have thinking about 18 degrees, we’re in no man’s land’” analyses from Bob Ebeling Thiokol




This quote was a very costly lesson in US NASA’s Space Shuttle history.  Seven astronauts lost their lives on a decision based on incomplete analysis.  The analysis and historical database did not include specific conditions that existed during Challenger’s launch on January 28, 1986.  Analysis allowed 40 oF and all previous launch temperatures were above 53 oF, NO analysis/data existed for below freezing temperatures.  Challenger’s launch temperature was about 28 oF.


During the post explosion investigation, we quickly learned about O-Rings:   joint seals between solid rocket booster sections.  “The causes of the accident fall into two categories: engineering problems related to design of the joint seal in the solid rocket booster, and flawed decision making procedures related to the launch of the shuttle”2..  Product development must look at the overall functionality/performance of a design but also whether the physical structure can support the design’s intended function and operating environment.  The Challenger explosion was due to a very small physical component in the shuttle program.  Much of the Challenger’s design was based on proven technologies. US Air Force’s Titan III rockets, what had a long, successful history, were used as a model for the Shuttle Solid Rocket Booster.  In this case historical successes can breed misplaced complacency.  For newer technologies, users must learn how components’ affect each other in their specific environment.  The next Space Shuttle would not be launched for 32 months as they resolved design, policies and management issues.


How does this translate to high technology products?  High Technology continually delivers

new levels of product functionality and performance by forcing innovative processes, materials, methodologies and tools into the Design and Supply Chains of providers.  The latest smart phones, tablets, eBooks, all coupled with innovative business models and content/app stores are just a few examples.   Continually ‘pushing’ the envelope is what “More than Moore’s Law” is about:  assembling and composing diverse technologies into a small footprint with minimal weight and power requirements.  “More than Moore” is supported by 2.5D or 3D packaging solutions using Package on Package (PoP), System in Package (SiP) and/or TSV/CGA interposers to dramatically shrink or completely eliminate a printed circuit board.


Consumers benefit from this increasing integration.  They purchase the latest high tech

‘gadget’ and are mesmerized by the functionality contained in a small device.  Consumers might be aggravated at dropped calls or batteries that need frequent recharging, but show off their latest purchase to anyone.  Most consumers are (and should be) oblivious to the complex technologies integrated into their products to provide these capabilities. This “state of mind” is more than a dream for consumers, it becomes their expectation.


This increased integration causes issues for product developers.  Product developers are faced with an infinite set of options and typically use pencil/paper, Excel spreadsheets, or some other – from today’s perspective – arcane method to ‘plan’ their product.  A growing number of development teams have migrated to Virtual Prototypes (VPs) to help visualize and analyze functionality and performance of these devices quickly and reliably.  VPs help analyze system performance based on hardware/software (HW/SW) trade-offs.  But these VPs are just a part of the solution and typically do not consider the physical structure required to support a product.  As with the O-Ring, if small components are incorrectly analyzed, catastrophic issues may come to light during a product’s launch into production.  Short lived euphoria can quickly turn into a nightmare for product developers.   They face high volume product commitments with little time to debug, fix and re-release the product.  Senior management quickly starts calculating the quarterly impact(s) to their P&L, sometimes quantifying the impact on a $s per day basis.  ALL involved hope the fix is easy to implement and can be injected late in the manufacturing process.  Their worst case fear:  re-design of the product from scratch3.


Are there methods to help analyze a design’s physical structure identifying potential “O-Ring” issues long before implementation?  The good news:  increasing levels of research are being performed at universities and research consortia concerning “More than Moore” challenges.  A new breed of tools is starting to emerge to aid developers in sorting out technical as well as business considerations.  They are called Path Finding tools.  Think of Path Finding as a Virtual Prototype for a design’s physical structure.   Path Finding tools can be applied to three failure mechanisms:  mechanical (stress), thermal (heat) and electrical (power distribution, signal integrity) concerns and can include cost estimates as well.  Each of these mechanisms must be accounted for in the physical structure of the design.  If structural analysis is inadequate, it does not matter what your VP predicted for system functionality and performance, failures occur


To be useful, Path Finding tools must be used EARLY in the planning phase.  Using a “post” implementation mentality similar to what is performed for Physical Verification (PV) is too late for these structural issues.   Path Finding will never replace PV.  Path Finding helps define how something should be implemented most reliable and cost-effective; this does not guarantee that the definition was implemented correctly.    For Path Finding to be valuable, it must provide the following:


  •  Accurate analysis
  •  Capable of analyzing the entire structure
  •  Fast creation and analysis of structures
  •  Capable of supporting many types of structures




Accurate analysis is paramount.  If the resulting analysis does not help guide the developer to rules/guidelines that allow a product to yield from manufacturing and normal use, it is a waste of time and money.  But accuracy must be based on the specific implementation.  The documented research4,5 states single via simulation cannot be extrapolated for the entire structure’s performance (mechanical, thermal or electrical).    A short example will be shown in the next section.


Capable of analyzing large structures is a key to accurate analysis.  Without being able to analyze the entire structure, mechanical and thermal interactions or signal integrity analysis

will not be accurate.  This is directly related how a design is modeled for analysis.  Many algorithms use a meshed structure which requires larger memory and CPU time as a design grows in size6.  Newer algorithms use “meshless” techniques requiring significantly less memory and CPU time enabling entire structures to be analyzed while preserving accuracy. This is especially critical for 2.5/3D packaging structures.  If vias are used, developers will maximize via usage within the design to maximize the benefits of:  power reduction; performance improvement; area requirements and even overall product costs.  As mentioned

above, accurate analysis is not one via at a time but ALL of them and their interactions at one time.


Fast creation and analysis allows users to quickly identify key manufacturing and/or physical implementation details that meet their specific design’s requirements.  Each design will have unique physical implementation and signaling that must be analyzed.  These constraints might require different implementation scenarios to be analyzed to determine allowable trade-offs.


Support various analyses.  Path Finding is about finding viable alternatives.  A Path Finder that is relegated to one analysis is less valuable than a Path Finder that can be used in many ways.  As an example, process tuning (also called Technology tuning) can be one aspect of Path Finding.  A manufacturer may want to perform Path Finding to help optimize their process for mechanical, thermal and electrical, focusing primarily on process parameters they will use

in their ‘process cook book’.  The same Path Finder could be used by a design team to help identify an optimal placement of design structures (i.e. vias) while holding various process parameters constant.  A design team that can vary both process and design variables has the ultimate flexibility but requires more analysis. More types of analysis supported allow a wider solution space to be explored for an optimum solution meeting cost, area, performance and power metrics.


Let us look at a short example of a 16 TSV arrayed structure (see Figure 1) related to signal integrity; a vital aspect to a structure’s performance.  A comparison is performed between a regular (Fig 1a) and a custom (Fig 1b) via pitched design.  Besides the via array layout, user also defines other parameters for analysis (Fig 1c).  The analysis will be performed on a Full Wave ElectroMagnetic (EM) Solver for accuracy.





Five variations were created and analyzed with various via dimensions and pitches.  Other manufacturing variables could have also been defined for a specific process but were held constant.  Figure 2a shows how Insertion Loss varies for each test structure.  Insertion Loss (IL) measures the signal’s degradation through the via.  The smaller the IL, the better the performance will be.  In this case the best is the 25um pitch, 15um tall, 2.5um diameter while the worst is 25um pitch, 60um tall and 2.5um diameter.  Comparing the five structures against each other for IL, at 4GHz, there is a 3x degradation variation and it continues to widen  as the frequency reaches 100GHz.  Depending on the application and signaling required, any of these variations might meet the requirements.  The variation chosen would both meet the requirements and be lowest in overall costs.


Figure 2b shows the Best and Worst Near End Cross Talk (NEXT) for the structures shown in Figure 1.  The NEXT analysis shows how much interference (noise) is transferred between a pair of vias.  The location of each via and physical distance from other vias will reflect different NEXT responses for each pair of vias.  Vias separated by larger distances will reflect less cross talk between them; closer vias will have larger cross talk.  From Figures 2b, variation is widest for the Custom version.  Some of the Custom NEXT responses are worse than the standard configuration but a few are better isolated.  Whether either will satisfy the goals of this specific design must be determined by the developer.  If both could satisfy the requirements the developer can choose the least costly option.



To view all NEXT responses would total 240, for Far End Cross Talk (FEXT) it would be an additional 240 responses for each structure.  To show the NEXT variation for one structure, Figure 3 shows responses for all the TOP vias; this totals 120 responses.  This analysis indicates that each unique physical distance between the vias causes a different noise response.  For the custom array, this has 25dB variation across all signals.  This indicates which via locations might be best suited for noise sensitive signals.  In addition this can help define signal to ground ratios as well as shielding needs.





 That is the beauty of path finding: objective data helps to compare different scenarios.   For an in depth Full Wave EM solver discussion, please refer to Prof. Swaminathan’s DesignCon2012



The above analysis was restricted to silicon interposers (TSV) and could easily have been expanded to include glass interposers (TGV) to understand the benefits and costs between the two solutions7.




Path Finding allows users a method to quickly analyze multiple solutions and choose the best one based upon:  cost, performance (mechanical, thermal and electrical), area and power.

Path Finding allows objective analysis to define how each design is constructed; it removes the

folklore or ‘gut’ instincts based on historical results.  2.5D/3D technologies have existed for years; as shown in the above example, each variation is unique and must be analyzed.  Path Finding methodology can accelerate the learning and reduce production risks; designing in reliability and costs effectiveness prior to physical verification or worst case on the production test floor.


2.5D/3D packaging technologies are revitalizing creativity in high technology products.  We thought we knew what faster, better, lighter and smaller meant.  2.5D/3D packaging can revolutionize what we thought possible but it will require augmenting our current methods and tools.  One key methodology to add would be Path Finding.   Path Finding can ensure a design’s structural integrity early in the development process and avoids finding issues that may be identified when it is too late to fix cheaply and quickly.


1.  Challenger and O-Rings operating in temperatures well below tested scenarios or historical usage.

Picture:  ”’  Space ShuttleChallenger” explodes shortly after take-off.

2.  Failure As A Design Criterion

3.  “Been there, done that”.  Long ago, we allowed an authorized design center to implement a design from specification into an ASIC.  When ASIC arrived, it did not work.  As we identified the failure’s root cause, we asked if this “component” was used elsewhere in the design.  “Yes, ~18 times” was the answer.  At that point, we realized a new design was required costing 6 calendar months, 12 engineering months and untold $’s.  The respun ASIC worked like a champ.

4.  Moongon Jung, Joydeep Mitra, David Z. Pan and Sung Kyu Lim, “TSV Stress-aware Full- Chip Mechanical Reliability Analysis and Optimization for 3D IC”.  DAC2011.

5.  Madhavan Swaminathan, “Electrical Design and Modeling Challenges for 3D System

Integration” DesignCon2012.

6.  Tony Abbey article “Meshing for FEA”.  Desktop Engineering January 2013.

  7.  Madhavan Swaminathan interview with Francois van Trapp entitled:”The Flip Side of the Glass Interposer Coin”.  3DinCites July 2012.



This is a guest post by Bill Martin, President / VP Engineering  of E-System Design


Marketing Tools for Silicon IP Vendors

Why You Need to Start Using AnySilicon’s IP Portal


In the past 4 months, AnySilicon has made the first steps into becoming an IP portal — to help both small and medium IP core suppliers with online marketing and lead generation efforts. As a result, AnySilicon platform enables now ASIC designs and managers to make smart decisions in early stage of any silicon project in search of both semiconductor service providers and IP core suppliers.


                                                                 Click here to see Sonics profile page



As the “last mover” in the IP portal domain, AnySilicon’s IP portal was built using various inputs from IP vendors, and learning from the existing solutions in the market. One of the most consistent feedback from IP vendors was regarding membership price which is already proven feature of AnySilicon website.



Top 5 Things You can Get from AnySilicon’s IP portal today!


Free IP listing

AnySilicon is still the cheapest and most affordable marketing and lead generation platform.  IP suppliers have a range of membership plans starting from free membership up to Gold membership. Get listed today here.


Dedicated Vendor Page

A dedicated vendor page lets you present your IP offering with visuals and additional material such as case studies, white papers, contact information and your social media handle. Your company information is embedded into our site search engine, allowing visitors searching for IP cores to find your vendor page using free text or by clicking on the pre-defined categories.


Qualified Leads

Compared to other websites, AnySilicon allows ASIC engineers and managers to browse our vendor directory and use the search tool without exposing their name. AnySilicon respect users privacy and therefore, users feeling more comfortable exploring and discovering IP cores on AnySilicon’s platform. Users are today more concern about their privacy and activity on the web so in the long run; this capability will bring more and more users to the platform.


Awareness and Branding

We help increasing your company profile and awareness via several marketing channels. We promote your company to our readers via our site, newsletter and social networks in a regular manner. This brings focus to your company products, logo and messaging. Links from your AnySilicon profile page to your website improves your website SEO ranking and bring more traffic to your website.


Cost Effective

Promoting your IPs AND services in one platform is the best way to reduce your marketing expenses cost and unnecessary overhead. Using AnySilicon platform to promote both IPs and semiconductor services in one marketing platform to save cost of double listing and the hassle of updating several platforms.



Want to learn more about AnySilicon membership plans that you can start using right away to engage with customers? Read more here. We’d love to help.


UMC Expects Wafer Shipment to Drop

UMC’s CEO, Po-Wen Yen, confirmed the drop of 5% on wafer shipment performance for the third quarter of 2015. The CEO justified this forecast  by referring to a restricted market visibility and to weaknesses in the demand due to the uncertain economic environment. Not only, Po-Wen-Yen mentioned also the inventory adjustments already announced at the beginning of the first quarter 2015 which are expected to last till the second half of the year.


Despite the foreseen drop in Q3-15, UMC registered a shipping record of 1.54 million 8-inch equivalent wafers in Q2. The company reached the incredible result of 94% of its production capacity mainly focusing on the 28nm products which, according to the official company’s statements, represent 11% of the company foundry current business. However, the 28mn technology has just recently started to receive attention from the market. Indeed, back in the same quarter of last year the same products were only reaching the 1% of the company’s demand and 9% during the first quarter of the year.


Taking a quick look back at the performance of the past 2 quarters of 2015, UMC generated revenues of US$1.23 billion for the second quarter. This result was 1% sequentially but down 6% compared to last year. Also the gross margins found a small inflection of 1.4% in contrast to the 24.3% registered in the first quarter and the 22.9% in second quarter 2014. However, we can’t help to notice the extraordinary result generated by UMC in net profits during the second quarter of 2015: NT$4.6 billion with the EPS arriving at NT$0.37. As predictable also second quarter revenues of UMC’s foundry business reached NT$36.52 billion and 25.1% gross margin.


As already prospected, the third quarter 2015 scenario is not as bright as the previous one. UMC expects to go under the 90% usage of its production capacity and, par consequences, shipments will drop in between 3 to 5%.


See here UMC profile page.